RV_TIMER Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.320s	19.532us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.370s	20.047us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.420s	44.551us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.430s	64.402us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.400s	33.337us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.610s	54.208us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.420s	44.551us	1	1	100.00
		rv_timer_csr_aliasing	1.400s	33.337us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	6.660s	5.112ms	1	1	100.00
V2	disabled	rv_timer_disabled	2.080s	2.630ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.580s	163.887us	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.580s	163.887us	1	1	100.00
V2	stress	rv_timer_stress_all	1.680s	58.325us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.440s	13.702us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.360s	34.318us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.930s	552.656us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.930s	552.656us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.370s	20.047us	1	1	100.00
		rv_timer_csr_rw	1.420s	44.551us	1	1	100.00
		rv_timer_csr_aliasing	1.400s	33.337us	1	1	100.00
		rv_timer_same_csr_outstanding	1.580s	106.567us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.370s	20.047us	1	1	100.00
		rv_timer_csr_rw	1.420s	44.551us	1	1	100.00
		rv_timer_csr_aliasing	1.400s	33.337us	1	1	100.00
		rv_timer_same_csr_outstanding	1.580s	106.567us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.600s	128.420us	1	1	100.00
		rv_timer_tl_intg_err	1.710s	364.267us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.710s	364.267us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	12.390s	1.601ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.420s	16.689us	1	1	100.00
		rv_timer_max	1.450s	72.230us	1	1	100.00
		TOTAL			19	19	100.00