SPI_DEVICE/1R1W Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	17.370s	4.109ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.120s	163.126us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.880s	43.499us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.040s	356.574us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.890s	1.243ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.480s	136.626us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.880s	43.499us	1	1	100.00
		spi_device_csr_aliasing	17.890s	1.243ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.570s	144.485us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.280s	39.892us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.740s	45.530us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.670s	6.233us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.710s	3.961us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.800s	306.222us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.800s	306.222us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.980s	123.367us	1	1	100.00
		spi_device_tpm_sts_read	2.340s	86.345us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	23.170s	6.610ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	10.620s	18.901ms	1	1	100.00
		spi_device_flash_all	1.505m	83.028ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.620s	35.295us	1	1	100.00
		spi_device_flash_all	1.505m	83.028ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.620s	35.295us	1	1	100.00
		spi_device_flash_all	1.505m	83.028ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.505m	83.028ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.950s	961.300us	1	1	100.00
		spi_device_flash_all	1.505m	83.028ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.950s	961.300us	1	1	100.00
		spi_device_flash_all	1.505m	83.028ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.950s	961.300us	1	1	100.00
		spi_device_flash_all	1.505m	83.028ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.950s	961.300us	1	1	100.00
		spi_device_flash_all	1.505m	83.028ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.950s	961.300us	1	1	100.00
		spi_device_flash_all	1.505m	83.028ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.500s	697.505us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.740s	96.320us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.740s	96.320us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.740s	96.320us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	5.460s	618.845us	1	1	100.00
		spi_device_read_buffer_direct	9.360s	1.567ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.740s	96.320us	1	1	100.00
		spi_device_flash_all	1.505m	83.028ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.505m	83.028ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.505m	83.028ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	7.420s	9.792ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	7.420s	9.792ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	17.370s	4.109ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	28.930s	10.440ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.880m	13.140ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.700s	14.271us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.720s	13.299us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.650s	814.691us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.650s	814.691us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.120s	163.126us	1	1	100.00
		spi_device_csr_rw	2.880s	43.499us	1	1	100.00
		spi_device_csr_aliasing	17.890s	1.243ms	1	1	100.00
		spi_device_same_csr_outstanding	2.770s	146.186us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.120s	163.126us	1	1	100.00
		spi_device_csr_rw	2.880s	43.499us	1	1	100.00
		spi_device_csr_aliasing	17.890s	1.243ms	1	1	100.00
		spi_device_same_csr_outstanding	2.770s	146.186us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.910s	160.284us	1	1	100.00
		spi_device_tl_intg_err	17.970s	2.276ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	17.970s	2.276ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.190s	309.145us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.26301783741387940706073614395084688026359778069956149467739998939870341449795
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3524336 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[17])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3524336 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3524336 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[913])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.84823816459543784390639721147589055244277732033899533008184382819414215958365
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1764071 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe72c85 [111001110010110010000101] vs 0x0 [0])
        UVM_ERROR @   1797071 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf86aa3 [111110000110101010100011] vs 0x0 [0])
        UVM_ERROR @   1799071 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe9d6e [11101001110101101110] vs 0x0 [0])
        UVM_ERROR @   1824071 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x855a74 [100001010101101001110100] vs 0x0 [0])
        UVM_ERROR @   1918071 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1cd64 [11100110101100100] vs 0x0 [0])