SPI_DEVICE/2P Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.006m	3.567ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.140s	30.298us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.070s	469.066us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.600s	2.783ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.590s	317.049us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.190s	414.184us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.070s	469.066us	1	1	100.00
		spi_device_csr_aliasing	6.590s	317.049us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.950s	18.363us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.590s	31.365us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.690s	79.746us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.860s	34.895us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.610s	18.011us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.080s	154.743us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.080s	154.743us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	9.790s	2.790ms	1	1	100.00
		spi_device_tpm_sts_read	1.700s	747.397us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.580s	37.384us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.030s	300.198us	1	1	100.00
		spi_device_flash_all	1.730s	20.983us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.490s	855.401us	1	1	100.00
		spi_device_flash_all	1.730s	20.983us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.490s	855.401us	1	1	100.00
		spi_device_flash_all	1.730s	20.983us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.730s	20.983us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.950s	821.443us	1	1	100.00
		spi_device_flash_all	1.730s	20.983us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.950s	821.443us	1	1	100.00
		spi_device_flash_all	1.730s	20.983us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.950s	821.443us	1	1	100.00
		spi_device_flash_all	1.730s	20.983us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.950s	821.443us	1	1	100.00
		spi_device_flash_all	1.730s	20.983us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.950s	821.443us	1	1	100.00
		spi_device_flash_all	1.730s	20.983us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	22.310s	11.196ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	5.620s	414.564us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	5.620s	414.564us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	5.620s	414.564us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	14.780s	7.700ms	1	1	100.00
		spi_device_read_buffer_direct	8.780s	2.122ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	5.620s	414.564us	1	1	100.00
		spi_device_flash_all	1.730s	20.983us	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.730s	20.983us	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.730s	20.983us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.700s	295.643us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.700s	295.643us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.006m	3.567ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.184m	31.304ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.069m	26.937ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.710s	36.963us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.660s	29.788us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.740s	32.540us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.740s	32.540us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.140s	30.298us	1	1	100.00
		spi_device_csr_rw	3.070s	469.066us	1	1	100.00
		spi_device_csr_aliasing	6.590s	317.049us	1	1	100.00
		spi_device_same_csr_outstanding	4.200s	70.733us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.140s	30.298us	1	1	100.00
		spi_device_csr_rw	3.070s	469.066us	1	1	100.00
		spi_device_csr_aliasing	6.590s	317.049us	1	1	100.00
		spi_device_same_csr_outstanding	4.200s	70.733us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.180s	108.495us	1	1	100.00
		spi_device_tl_intg_err	6.610s	560.117us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.610s	560.117us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	23.170s	14.587ms	1	1	100.00
		TOTAL			33	33	100.00