SRAM_CTRL/MAIN Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	35.480s	905.220us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.590s	110.893us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.580s	16.605us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.330s	257.798us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.540s	16.322us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.650s	354.256us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.580s	16.605us	1	1	100.00
		sram_ctrl_csr_aliasing	1.540s	16.322us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.406m	147.953ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.093m	24.204ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.678m	6.609ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.017m	9.244ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	18.692m	23.576ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.332m	48.401ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	24.370s	5.316ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.854m	85.460ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	4.980s	2.815ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.073m	58.251ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	11.650s	714.165us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	59.030s	1.572ms	1	1	100.00
		sram_ctrl_throughput_w_readback	46.230s	902.529us	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.327m	1.866ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.080s	712.054us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	57.123m	170.918ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.590s	19.929us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.830s	283.648us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.830s	283.648us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.590s	110.893us	1	1	100.00
		sram_ctrl_csr_rw	1.580s	16.605us	1	1	100.00
		sram_ctrl_csr_aliasing	1.540s	16.322us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	16.309us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.590s	110.893us	1	1	100.00
		sram_ctrl_csr_rw	1.580s	16.605us	1	1	100.00
		sram_ctrl_csr_aliasing	1.540s	16.322us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	16.309us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	33.590s	27.154ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.560s	5.027us	0	1	0.00
		sram_ctrl_tl_intg_err	2.400s	206.029us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.560s	5.027us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.400s	206.029us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.327m	1.866ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.327m	1.866ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.580s	16.605us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.854m	85.460ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.854m	85.460ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.854m	85.460ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	24.370s	5.316ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.630s	1.334ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	33.590s	27.154ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.660s	671.966us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	35.480s	905.220us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	35.480s	905.220us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.854m	85.460ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.560s	5.027us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	24.370s	5.316ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.560s	5.027us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.560s	5.027us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	35.480s	905.220us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.560s	5.027us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	49.240s	3.610ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.98364444637658386178623284549330378350409005050057390179273059499151847808906
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   5026699 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   5026699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---