SRAM_CTRL/RET Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	23.440s	1.873ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.550s	29.311us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.570s	28.335us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.840s	98.437us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.530s	50.378us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.440s	58.525us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.570s	28.335us	1	1	100.00
		sram_ctrl_csr_aliasing	1.530s	50.378us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.570s	462.268us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.280s	377.558us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.831m	12.733ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.456m	2.191ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	25.540s	11.684ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.978m	8.554ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.410s	2.472ms	1	1	100.00
V2	executable	sram_ctrl_executable	9.600m	6.356ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	51.870s	302.571us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.321m	148.649ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	26.770s	111.286us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	25.730s	131.535us	1	1	100.00
		sram_ctrl_throughput_w_readback	12.680s	615.870us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.562m	9.186ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.600s	88.787us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	34.996m	45.387ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.630s	28.000us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.970s	145.694us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.970s	145.694us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.550s	29.311us	1	1	100.00
		sram_ctrl_csr_rw	1.570s	28.335us	1	1	100.00
		sram_ctrl_csr_aliasing	1.530s	50.378us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.720s	23.224us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.550s	29.311us	1	1	100.00
		sram_ctrl_csr_rw	1.570s	28.335us	1	1	100.00
		sram_ctrl_csr_aliasing	1.530s	50.378us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.720s	23.224us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.730s	788.361us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.720s	2.840us	0	1	0.00
		sram_ctrl_tl_intg_err	2.120s	214.155us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.720s	2.840us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.120s	214.155us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.562m	9.186ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.562m	9.186ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.570s	28.335us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	9.600m	6.356ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	9.600m	6.356ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	9.600m	6.356ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.410s	2.472ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.790s	173.265us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.730s	788.361us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.110s	44.097us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	23.440s	1.873ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	23.440s	1.873ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	9.600m	6.356ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.720s	2.840us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.410s	2.472ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.720s	2.840us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.720s	2.840us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	23.440s	1.873ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.720s	2.840us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.856m	11.362ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.107268881243969100280968270108561627728240921905646238589558848507267825645145
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2839657 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2839657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---