SYSRST_CTRL Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 5.670s 2.109ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 4.900s 2.452ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 4.150s 2.409ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 8.390s 2.544ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 4.770s 6.090ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 3.680s 2.109ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 10.600s 39.326ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 8.200s 2.823ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.840s 2.130ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 3.680s 2.109ms 1 1 100.00
sysrst_ctrl_csr_aliasing 8.200s 2.823ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.437m 176.549ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 3.275m 111.999ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 3.290s 3.464ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 2.960s 2.626ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 2.040s 2.690ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 5.670s 2.126ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 3.140s 5.019ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 4.870s 2.623ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 3.360s 14.792ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 32.920s 36.985ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 3.771m 217.592ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 3.300s 2.021ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 3.350s 2.027ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.920s 2.098ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.920s 2.098ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 4.770s 6.090ms 1 1 100.00
sysrst_ctrl_csr_rw 3.680s 2.109ms 1 1 100.00
sysrst_ctrl_csr_aliasing 8.200s 2.823ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.040s 4.271ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 4.770s 6.090ms 1 1 100.00
sysrst_ctrl_csr_rw 3.680s 2.109ms 1 1 100.00
sysrst_ctrl_csr_aliasing 8.200s 2.823ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.040s 4.271ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 1.238m 42.008ms 1 1 100.00
sysrst_ctrl_tl_intg_err 1.414m 42.358ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.414m 42.358ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 5.380s 7.056ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00