UART Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.160s	649.977us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.840s	16.724us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.510s	18.246us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.710s	673.179us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.470s	20.021us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.550s	20.447us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.510s	18.246us	1	1	100.00
		uart_csr_aliasing	1.470s	20.021us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	3.510s	9.764ms	1	1	100.00
V2	parity	uart_smoke	2.160s	649.977us	1	1	100.00
		uart_tx_rx	3.510s	9.764ms	1	1	100.00
V2	parity_error	uart_intr	8.910s	37.306ms	1	1	100.00
		uart_rx_parity_err	31.360s	91.794ms	1	1	100.00
V2	watermark	uart_tx_rx	3.510s	9.764ms	1	1	100.00
		uart_intr	8.910s	37.306ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.022m	177.267ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	50.450s	42.510ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	34.240s	85.527ms	1	1	100.00
V2	rx_frame_err	uart_intr	8.910s	37.306ms	1	1	100.00
V2	rx_break_err	uart_intr	8.910s	37.306ms	1	1	100.00
V2	rx_timeout	uart_intr	8.910s	37.306ms	1	1	100.00
V2	perf	uart_perf	59.070s	18.979ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.350s	8.548ms	1	1	100.00
V2	line_loopback	uart_loopback	2.350s	8.548ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	18.110s	29.980ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	7.560s	4.700ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.130s	1.955ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	2.930s	3.070ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.241m	172.327ms	1	1	100.00
V2	stress_all	uart_stress_all	52.110s	36.486ms	1	1	100.00
V2	alert_test	uart_alert_test	1.530s	12.417us	1	1	100.00
V2	intr_test	uart_intr_test	1.720s	17.517us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.060s	75.133us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.060s	75.133us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.840s	16.724us	1	1	100.00
		uart_csr_rw	1.510s	18.246us	1	1	100.00
		uart_csr_aliasing	1.470s	20.021us	1	1	100.00
		uart_same_csr_outstanding	1.550s	80.767us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.840s	16.724us	1	1	100.00
		uart_csr_rw	1.510s	18.246us	1	1	100.00
		uart_csr_aliasing	1.470s	20.021us	1	1	100.00
		uart_same_csr_outstanding	1.550s	80.767us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.900s	69.625us	1	1	100.00
		uart_tl_intg_err	2.240s	375.466us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.240s	375.466us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	26.720s	6.558ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00