CHIP Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: `608ba69`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.566m	2.742ms	1	1	100.00
		chip_sw_example_rom	1.462m	3.158ms	1	1	100.00
		chip_sw_example_manufacturer	2.031m	2.380ms	1	1	100.00
		chip_sw_example_concurrency	2.581m	2.785ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.795m	8.153ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.999m	6.608ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	3.719m	4.465ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	52.538m	26.153ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	44.210s	2.661ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	52.538m	26.153ms	1	1	100.00
		chip_csr_rw	5.999m	6.608ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.800s	33.833us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	3.884m	3.982ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	3.884m	3.982ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	3.884m	3.982ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.538m	4.081ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.538m	4.081ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.210m	3.992ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.470m	4.651ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.115m	4.473ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.823m	8.203ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.910m	4.604ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	17.186m	13.160ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.522m	3.941ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.522m	3.941ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.990m	3.396ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.570m	3.507ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.265m	4.393ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	11.946m	11.854ms	1	1	100.00
		chip_tap_straps_testunlock0	1.778m	2.516ms	1	1	100.00
		chip_tap_straps_rma	8.446m	9.472ms	1	1	100.00
		chip_tap_straps_prod	1.449m	3.293ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.388m	2.715ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.440m	9.325ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.662m	5.465ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.662m	5.465ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.427m	7.314ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	30.024m	20.274ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.417m	4.499ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.528m	5.736ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.692m	17.759ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.127m	2.503ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.408m	7.114ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.236m	2.441ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.032m	9.408ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.470m	3.037ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.749m	5.715ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.880m	3.141ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.438m	2.710ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	4.669m	4.750ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.503m	4.400ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.392m	2.914ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.503m	4.400ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.671m	3.281ms	1	1	100.00
		chip_sw_aes_smoketest	2.728m	2.928ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.487m	3.131ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.066m	2.546ms	1	1	100.00
		chip_sw_csrng_smoketest	2.910m	3.703ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.588m	3.398ms	1	1	100.00
		chip_sw_gpio_smoketest	2.778m	2.890ms	1	1	100.00
		chip_sw_hmac_smoketest	2.794m	3.423ms	1	1	100.00
		chip_sw_kmac_smoketest	3.226m	3.187ms	1	1	100.00
		chip_sw_otbn_smoketest	17.020m	9.680ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.276m	4.955ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.496m	5.099ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.317m	3.285ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.679m	2.844ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.425m	2.264ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.595m	2.256ms	1	1	100.00
		chip_sw_uart_smoketest	2.747m	3.214ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.779m	3.016ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.075m	4.087ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.956h	60.218ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.103m	15.387ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.557m	6.018ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.111m	3.290ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.276m	3.093ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.860h	52.924ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.950h	58.069ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	43.240s	2.555ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	43.240s	2.555ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	52.538m	26.153ms	1	1	100.00
		chip_same_csr_outstanding	30.827m	27.363ms	1	1	100.00
		chip_csr_hw_reset	3.795m	8.153ms	1	1	100.00
		chip_csr_rw	5.999m	6.608ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	52.538m	26.153ms	1	1	100.00
		chip_same_csr_outstanding	30.827m	27.363ms	1	1	100.00
		chip_csr_hw_reset	3.795m	8.153ms	1	1	100.00
		chip_csr_rw	5.999m	6.608ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	28.490s	379.426us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.360s	43.123us	1	1	100.00
		xbar_smoke_large_delays	37.310s	5.975ms	1	1	100.00
		xbar_smoke_slow_rsp	47.090s	3.547ms	1	1	100.00
		xbar_random_zero_delays	35.480s	622.532us	1	1	100.00
		xbar_random_large_delays	2.653m	28.861ms	1	1	100.00
		xbar_random_slow_rsp	34.580s	3.716ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	33.930s	1.261ms	1	1	100.00
		xbar_error_and_unmapped_addr	13.620s	453.533us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	7.950s	101.980us	1	1	100.00
		xbar_error_and_unmapped_addr	13.620s	453.533us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	55.910s	2.224ms	1	1	100.00
		xbar_access_same_device_slow_rsp	55.050s	5.628ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	41.300s	2.254ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	41.220s	738.825us	1	1	100.00
		xbar_stress_all_with_error	1.300m	1.560ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	51.870s	375.031us	1	1	100.00
		xbar_stress_all_with_reset_error	2.102m	850.626us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.103m	15.387ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	35.966m	28.516ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.308m	14.258ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.867m	10.863ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.339m	15.078ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	38.309m	15.488ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	41.052m	15.308ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	39.157m	14.644ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.660s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	31.010s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	28.200s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	31.640s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	34.250s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.640s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	30.110s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	26.830s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26.710s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.060s	10.260us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.830s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.670s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	27.770s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	26.610s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	27.890s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.570s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.980s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	27.130s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	27.990s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	27.910s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.310s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.890s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.990s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	28.150s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	26.050s	10.160us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.670m	10.722ms	1	1	100.00
		rom_e2e_asm_init_dev	38.439m	16.041ms	1	1	100.00
		rom_e2e_asm_init_prod	36.526m	15.856ms	1	1	100.00
		rom_e2e_asm_init_prod_end	37.051m	15.635ms	1	1	100.00
		rom_e2e_asm_init_rma	36.008m	14.766ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.965m	14.530ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.706m	15.155ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.609m	15.041ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.556m	15.681ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.882m	34.857ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.882m	34.857ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.325m	2.257ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.127m	2.503ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.719m	2.827ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.055m	3.053ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	13.150m	7.294ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.031m	3.571ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	3.795m	5.393ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.604m	5.528ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.638m	5.806ms	1	1	100.00
		chip_plic_all_irqs_10	4.228m	2.984ms	1	1	100.00
		chip_plic_all_irqs_20	5.576m	4.614ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.562m	2.977ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.231m	10.866ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.069m	3.886ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.551m	3.304ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.737m	12.082ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.288m	8.287ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.919m	7.248ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.515m	8.225ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.108h	255.553ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.955m	4.084ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.276m	4.955ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.955m	4.084ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.601m	9.878ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.601m	9.878ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.360m	7.101ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.823m	4.867ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.258m	5.965ms	1	1	100.00
		chip_sw_aes_idle	2.055m	3.053ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.237m	2.215ms	1	1	100.00
		chip_sw_kmac_idle	2.719m	2.966ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.194m	3.542ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.800m	5.289ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.094m	5.393ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.081m	4.114ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	13.774m	11.292ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.294m	3.727ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.218m	5.073ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.561m	3.653ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.583m	4.393ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.342m	4.048ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.740m	5.003ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.427m	7.314ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.000m	13.024ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.561m	3.653ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.583m	4.393ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.417m	4.499ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.528m	5.736ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.692m	17.759ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.127m	2.503ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.408m	7.114ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.236m	2.441ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.032m	9.408ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.470m	3.037ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.749m	5.715ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.880m	3.141ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.874m	3.160ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.784m	4.114ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.679m	7.524ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.446m	23.664ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.015m	2.853ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.554m	2.543ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	17.185m	11.539ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.113m	3.361ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.100m	4.407ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	19.228m	24.267ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	30.733m	16.982ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.427m	7.314ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.504m	4.105ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.360m	3.509ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.604m	5.528ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.288m	8.287ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	10.141m	6.428ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.277m	2.649ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	7.638m	7.565ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.008m	2.740ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	56.454m	21.650ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.720m	2.511ms	1	1	100.00
		chip_sw_edn_entropy_reqs	8.523m	5.979ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.720m	2.511ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	10.141m	6.428ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.599m	2.834ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	17.895m	22.643ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.613m	5.338ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.528m	5.736ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.223m	3.984ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.417m	4.499ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	53.011m	43.463ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	17.895m	22.643ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.247m	3.483ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	18.595m	9.262ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.032m	4.225ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	53.011m	43.463ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.032m	4.225ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.032m	4.225ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.032m	4.225ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.032m	4.225ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.604m	5.528ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.708m	4.940ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.636m	4.941ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.626m	4.419ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.626m	4.419ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.722m	2.698ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.236m	2.441ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.237m	2.215ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.821m	2.926ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	14.998m	8.664ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.267m	5.422ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	4.957m	4.469ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.643m	5.077ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.395m	3.212ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	18.595m	9.262ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.032m	9.408ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	11.239m	7.701ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	13.150m	7.294ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	32.866m	12.755ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.027m	3.392ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.737m	3.352ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.470m	3.037ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	18.595m	9.262ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.691m	5.055ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.286m	2.732ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	22.670m	10.615ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.719m	2.966ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	3.795m	5.393ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	11.946m	11.854ms	1	1	100.00
		chip_tap_straps_rma	8.446m	9.472ms	1	1	100.00
		chip_tap_straps_prod	1.449m	3.293ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.369m	2.850ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.691m	5.055ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.691m	5.055ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.691m	5.055ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	16.683m	9.449ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.032m	4.225ms	1	1	100.00
		chip_sw_flash_rma_unlocked	53.011m	43.463ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.990m	3.408ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.300m	6.143ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.275m	5.770ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.409m	6.130ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.691m	5.055ms	1	1	100.00
		chip_sw_keymgr_key_derivation	18.595m	9.262ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.289m	9.781ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.417m	7.906ms	1	1	100.00
		chip_prim_tl_access	1.708m	4.940ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.000m	13.024ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.294m	3.727ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.218m	5.073ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.561m	3.653ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.583m	4.393ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.342m	4.048ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.740m	5.003ms	1	1	100.00
		chip_tap_straps_dev	11.946m	11.854ms	1	1	100.00
		chip_tap_straps_rma	8.446m	9.472ms	1	1	100.00
		chip_tap_straps_prod	1.449m	3.293ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.518m	12.609ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.647m	3.692ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.468m	3.932ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.396m	2.625ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.097m	3.316ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.397m	26.379ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.518m	12.609ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	57.341m	47.358ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.085h	49.157ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.279m	10.249ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	56.093m	48.799ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	21.397m	26.379ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.129m	2.400ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.252m	3.077ms	1	1	100.00
		rom_volatile_raw_unlock	1.380m	2.684ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	52.458m	16.162ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.692m	17.759ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.258m	5.965ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.258m	5.965ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.258m	5.965ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.615m	3.420ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.691m	5.055ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	17.895m	22.643ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.615m	3.420ms	1	1	100.00
		chip_sw_keymgr_key_derivation	18.595m	9.262ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.013m	4.715ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.369m	3.025ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	17.895m	22.643ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.615m	3.420ms	1	1	100.00
		chip_sw_keymgr_key_derivation	18.595m	9.262ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.013m	4.715ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.369m	3.025ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.691m	5.055ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.931m	3.846ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.369m	2.850ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.990m	3.408ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.300m	6.143ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.275m	5.770ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.409m	6.130ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.691m	5.055ms	1	1	100.00
		chip_prim_tl_access	1.708m	4.940ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.708m	4.940ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.995m	8.565ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.171m	7.716ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	15.846m	27.948ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.604m	7.395ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.601m	8.949ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.242m	7.521ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	18.585m	22.061ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.888m	13.162ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.601m	9.878ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	8.876m	8.038ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.955m	4.284ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.171m	7.716ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.124m	3.796ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	32.765m	32.065ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.842m	6.470ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.322m	4.925ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.062m	23.264ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.889m	7.082ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	15.640m	11.022ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	26.009m	23.797ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.862m	2.979ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.604m	5.528ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.289m	9.781ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.289m	9.781ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	15.640m	11.022ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.062m	23.264ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.955m	4.284ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.276m	4.955ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.755m	4.330ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.425m	4.526ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.550m	5.042ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.231m	10.866ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.551m	2.861ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.604m	5.528ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	12.919m	7.248ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.292m	5.244ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.332m	4.644ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.413m	2.505ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.369m	3.025ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.425m	4.526ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.425m	4.526ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	18.890m	19.238ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.409m	13.336ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.755m	4.330ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.393m	4.745ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.673m	6.550ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	8.446m	9.472ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.518m	12.609ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.638m	5.806ms	1	1	100.00
		chip_plic_all_irqs_10	4.228m	2.984ms	1	1	100.00
		chip_plic_all_irqs_20	5.576m	4.614ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.605m	3.176ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.703m	2.957ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.103m	15.387ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.244m	5.878ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.213m	2.606ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.846m	3.420ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.211m	3.185ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.013m	4.715ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.749m	5.715ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.096m	8.123ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	4.952m	7.733ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.417m	7.906ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.604m	5.528ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.662m	5.465ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.889m	7.082ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	19.013m	24.142ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.865m	3.007ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.446m	2.867ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.171m	3.995ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	19.013m	24.142ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	19.013m	24.142ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	38.727m	20.973ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	38.727m	20.973ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.984m	4.965ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.882m	34.857ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.498m	2.383ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.254m	2.438ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.696m	3.688ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.921m	3.808ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.458m	8.270ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.317h	31.601ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	28.162m	11.934ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	1.788m	2.439ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.220m	2.708ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.084m	2.929ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.436h	71.758ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.635m	3.289ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.432m	11.116ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.769m	11.952ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.114m	10.898ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.394m	3.521ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.171m	4.461ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.354m	3.718ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	15.212s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.916m	5.352ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.784m	2.940ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	11.422m	4.785ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	16.982m	7.378ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.124m	2.305ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.554m	5.333ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.316m	2.182ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	7.229m	6.037ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.777m	6.164ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.852m	5.506ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	15.640m	11.022ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.432m	11.116ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.769m	11.952ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.114m	10.898ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.027m	5.601ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.604m	5.528ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.446h	38.532ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.446h	38.532ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.073m	3.692ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.538m	4.081ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	48.839m	18.854ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.694m	3.102ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.717m	5.848ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.492m	3.139ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.177m	2.924ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.008m	3.256ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.888s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.990m	3.165ms	1	1	100.00
		TOTAL			285	325	87.69

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.65387791387864110813545368178865251108308453706030137589467481879029835424150
    Line 636, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.73130871934019167885318485697000584048432033812783564264444955493050378150589
    Line 636, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.74108762736020443158174639772769599451418969401249376955273760591154707649233
    Line 681, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.67562697364069342653633199547136951558066425312656291211912938479507702883298
    Line 733, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.84135092422042098826245174545414096207977448200655931268703143816238179707166
    Line 677, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.37626651585020360537658927201275904254014601847360631660971741445459371970599
    Line 614, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.99274948993441721359843592380353770234794655591311565065346287477256439684060
    Line 634, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.95492009443085850369183063272951097728491246472725019591732462613352352516537
    Line 618, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.29464947964615112712091393618450378659263224941146294141705127934786594468382
    Line 634, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.98240286715019677849385820129432512095525232092680361809477476562959161946545
    Line 638, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.108115729532106637153698505663028395276191393474127142784855676880773948474135
    Line 623, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.55467049228231167314406882581523332118757353563727080707289776491719860279467
    Line 726, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.18965422712338064249253305386621339324177475435177129110143262521553569486714
    Line 648, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.114377879718521129774191930916455744153019671329188514403749413055826642384344
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.344s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.107743093118172607763275362891816016156223600309145053661154746786571824454567
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 3.394s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.104867543388506879674315538866092214713753387494490994819092498499670662046901
    Line 825, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.25657565106411146577332990533394341030726353911403942648119617103175202791063
    Line 645, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.58509070046697095454428874573310239298030363274919882343603132476142071811503
    Line 900, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.55993983008419512079575323620763332662799030506102537214459530128730315386265
    Line 727, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.31188611689289975281654549235583085087689894908445491448848977047317759702269
    Line 442, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2605.540360 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2605.540360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@84357) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.94659314470682552231604149412119669142736067517851807445364299374848455381025
Line 444, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4526.178804 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@84357) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4526.178804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.840585058412084647768394841643732232268657138395715563747540086035448230301
    Line 438, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34856.528053 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34856.528053 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.20734226938044615572299794563257349260122631453086826713894672252793412038801
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3570.951276 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 3570.951276 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.56619715439684505228086223387039688701564301502933296356622283557177365895860
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3303.706336 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3303.706336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.43011343111796575276456719049068298254997082167153060407128459174444721785888
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2649.373860 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2649.373860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32377) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.49027097112659068786380309709048816203027851401690185089885236520809791891632
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2554.938784 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32377) { a_addr: 'h1044c  a_data: 'hb62293d5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h4  a_user: 'h1a501  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2554.938784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.48277151318415314835396081971727336626990974206783944578135262472584570073572
    Line 437, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2928.863184 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2928.863184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.17070267888664885765893689227516023984111728984667233477708845032328646918058
    Line 425, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3290.245000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3290.245000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.17117488643596949054382189983293356764217255833997374264571482460803846888399
    Line 435, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3093.405000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3093.405000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.56891211966261005780152614222766126176969395641752103985873619142739881486960
    Line 445, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 20273.939525 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 20273.939525 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.113038456712126539368056027822418465446559242959041028102048541082495436768545
    Line 474, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3289.221767 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3289.221767 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.19904101204357148756174868755485105529020459117164679158509728423756089128450
    Line 696, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.95281223865616256219304051561063559948631272647187033635152789580538742782048
    Line 690, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31803) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.22741959895463261031707322076872560212929380553024249052424223298166390054610
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2660.764104 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31803) { a_addr: 'h10664  a_data: 'hb63080d5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h4  a_user: 'h1a260  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2660.764104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---