ADC_CTRL Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	4.540s	5.918ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.080s	667.778us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.950s	548.070us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	27.340s	27.367ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.000s	973.584us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.790s	446.381us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.950s	548.070us	1	1	100.00
		adc_ctrl_csr_aliasing	3.000s	973.584us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	10.287m	491.592ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1.179m	166.834ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	29.710s	165.924ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	6.644m	487.464ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	14.249m	534.705ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.414m	203.374ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.363m	89.750ms	0	1	0.00
V2	clock_gating	adc_ctrl_clock_gating	2.445m	364.901ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	5.470s	4.756ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	14.730s	30.409ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.534m	110.395ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	37.990s	183.578ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.910s	309.305us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.420s	404.460us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.140s	1.326ms	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.140s	1.326ms	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.080s	667.778us	1	1	100.00
		adc_ctrl_csr_rw	1.950s	548.070us	1	1	100.00
		adc_ctrl_csr_aliasing	3.000s	973.584us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.310s	2.476ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.080s	667.778us	1	1	100.00
		adc_ctrl_csr_rw	1.950s	548.070us	1	1	100.00
		adc_ctrl_csr_aliasing	3.000s	973.584us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.310s	2.476ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	3.050s	4.485ms	1	1	100.00
		adc_ctrl_tl_intg_err	9.810s	4.534ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	9.810s	4.534ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	3.490s	3.188ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 0.adc_ctrl_filters_both.28765917930291450144823890260197517912909310250974521856378757036450910545525
      Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest/run.log

        UVM_ERROR @ 89750029118 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 89750029118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---