EDN Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.950s	32.224us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.550s	14.338us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.840s	12.263us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.100s	97.642us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.820s	51.175us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.750s	27.942us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.840s	12.263us	1	1	100.00
		edn_csr_aliasing	1.820s	51.175us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.230s	60.375us	1	1	100.00
V2	csrng_commands	edn_genbits	2.230s	60.375us	1	1	100.00
V2	genbits	edn_genbits	2.230s	60.375us	1	1	100.00
V2	interrupts	edn_intr	1.900s	28.136us	1	1	100.00
V2	alerts	edn_alert	1.950s	117.640us	1	1	100.00
V2	errs	edn_err	1.930s	57.684us	1	1	100.00
V2	disable	edn_disable	2.050s	11.714us	1	1	100.00
		edn_disable_auto_req_mode	1.790s	23.805us	1	1	100.00
V2	stress_all	edn_stress_all	1.860s	57.695us	1	1	100.00
V2	intr_test	edn_intr_test	1.650s	23.895us	1	1	100.00
V2	alert_test	edn_alert_test	1.660s	48.436us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.510s	123.885us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.510s	123.885us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.550s	14.338us	1	1	100.00
		edn_csr_rw	1.840s	12.263us	1	1	100.00
		edn_csr_aliasing	1.820s	51.175us	1	1	100.00
		edn_same_csr_outstanding	1.640s	57.569us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.550s	14.338us	1	1	100.00
		edn_csr_rw	1.840s	12.263us	1	1	100.00
		edn_csr_aliasing	1.820s	51.175us	1	1	100.00
		edn_same_csr_outstanding	1.640s	57.569us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.840s	1.994ms	1	1	100.00
		edn_tl_intg_err	2.500s	238.365us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.840s	21.829us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.950s	117.640us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.840s	1.994ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.840s	1.994ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.840s	1.994ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.840s	1.994ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.950s	117.640us	1	1	100.00
		edn_sec_cm	6.840s	1.994ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.950s	117.640us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.500s	238.365us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	59.760s	23.616ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00