HMAC Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 6.530s 184.763us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.550s 40.957us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.410s 38.507us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 5.040s 1.957ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.060s 120.029us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.970s 29.478us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.410s 38.507us 1 1 100.00
hmac_csr_aliasing 3.060s 120.029us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.357m 2.117ms 1 1 100.00
V2 back_pressure hmac_back_pressure 39.610s 2.660ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.590s 180.436us 1 1 100.00
hmac_test_sha384_vectors 18.720s 221.007us 1 1 100.00
hmac_test_sha512_vectors 19.940s 3.492ms 1 1 100.00
hmac_test_hmac256_vectors 7.300s 448.335us 1 1 100.00
hmac_test_hmac384_vectors 9.280s 317.454us 1 1 100.00
hmac_test_hmac512_vectors 9.780s 1.643ms 1 1 100.00
V2 burst_wr hmac_burst_wr 22.880s 7.690ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 47.360s 512.744us 1 1 100.00
V2 error hmac_error 31.330s 10.847ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 39.900s 13.417ms 1 1 100.00
V2 save_and_restore hmac_smoke 6.530s 184.763us 1 1 100.00
hmac_long_msg 1.357m 2.117ms 1 1 100.00
hmac_back_pressure 39.610s 2.660ms 1 1 100.00
hmac_datapath_stress 47.360s 512.744us 1 1 100.00
hmac_burst_wr 22.880s 7.690ms 1 1 100.00
hmac_stress_all 1.742m 2.911ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 6.530s 184.763us 1 1 100.00
hmac_long_msg 1.357m 2.117ms 1 1 100.00
hmac_back_pressure 39.610s 2.660ms 1 1 100.00
hmac_datapath_stress 47.360s 512.744us 1 1 100.00
hmac_wipe_secret 39.900s 13.417ms 1 1 100.00
hmac_test_sha256_vectors 8.590s 180.436us 1 1 100.00
hmac_test_sha384_vectors 18.720s 221.007us 1 1 100.00
hmac_test_sha512_vectors 19.940s 3.492ms 1 1 100.00
hmac_test_hmac256_vectors 7.300s 448.335us 1 1 100.00
hmac_test_hmac384_vectors 9.280s 317.454us 1 1 100.00
hmac_test_hmac512_vectors 9.780s 1.643ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 6.530s 184.763us 1 1 100.00
hmac_long_msg 1.357m 2.117ms 1 1 100.00
hmac_back_pressure 39.610s 2.660ms 1 1 100.00
hmac_datapath_stress 47.360s 512.744us 1 1 100.00
hmac_burst_wr 22.880s 7.690ms 1 1 100.00
hmac_error 31.330s 10.847ms 1 1 100.00
hmac_wipe_secret 39.900s 13.417ms 1 1 100.00
hmac_test_sha256_vectors 8.590s 180.436us 1 1 100.00
hmac_test_sha384_vectors 18.720s 221.007us 1 1 100.00
hmac_test_sha512_vectors 19.940s 3.492ms 1 1 100.00
hmac_test_hmac256_vectors 7.300s 448.335us 1 1 100.00
hmac_test_hmac384_vectors 9.280s 317.454us 1 1 100.00
hmac_test_hmac512_vectors 9.780s 1.643ms 1 1 100.00
hmac_stress_all 1.742m 2.911ms 1 1 100.00
V2 stress_all hmac_stress_all 1.742m 2.911ms 1 1 100.00
V2 alert_test hmac_alert_test 1.410s 70.500us 1 1 100.00
V2 intr_test hmac_intr_test 1.500s 93.679us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.890s 826.880us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.890s 826.880us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.550s 40.957us 1 1 100.00
hmac_csr_rw 1.410s 38.507us 1 1 100.00
hmac_csr_aliasing 3.060s 120.029us 1 1 100.00
hmac_same_csr_outstanding 2.050s 99.718us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.550s 40.957us 1 1 100.00
hmac_csr_rw 1.410s 38.507us 1 1 100.00
hmac_csr_aliasing 3.060s 120.029us 1 1 100.00
hmac_same_csr_outstanding 2.050s 99.718us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.730s 142.172us 1 1 100.00
hmac_tl_intg_err 3.860s 139.744us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.860s 139.744us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 6.530s 184.763us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.860s 1.029ms 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 39.670s 2.840ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 4.470s 2.249ms 1 1 100.00
TOTAL 28 28 100.00