I2C Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: `b21d4d7`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	16.450s	1.216ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	14.030s	3.449ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.740s	75.984us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.690s	57.694us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.940s	380.535us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.920s	871.905us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.840s	35.206us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.690s	57.694us	1	1	100.00
		i2c_csr_aliasing	1.920s	871.905us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	5.140s	234.454us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	6.626m	18.140ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	10.570s	526.245us	1	1	100.00
V2	host_override	i2c_host_override	1.620s	16.284us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.420m	23.305ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.627m	7.903ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.190s	468.973us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.110s	269.283us	1	1	100.00
		i2c_host_fifo_reset_rx	3.600s	652.180us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	38.870s	16.612ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	6.150s	1.075ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.230s	106.400us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.810s	2.288ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	5.128m	35.922ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.330s	1.283ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	11.800s	3.553ms	1	1	100.00
		i2c_target_intr_smoke	8.870s	1.292ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.000s	198.941us	1	1	100.00
		i2c_target_fifo_reset_tx	2.090s	2.609ms	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	39.660s	38.263ms	1	1	100.00
		i2c_target_stress_rd	11.800s	3.553ms	1	1	100.00
		i2c_target_intr_stress_wr	3.184m	18.953ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.410s	1.342ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.112m	3.574ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.520s	817.201us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	19.250s	10.147ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.320s	186.839us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.280s	177.598us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	10.570s	526.245us	1	1	100.00
		i2c_host_perf_precise	7.260s	434.988us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	6.150s	1.075ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.210s	65.761us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.730s	580.368us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.810s	1.458ms	1	1	100.00
		i2c_target_nack_txstretch	2.060s	2.991ms	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.050s	248.196us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.800s	477.708us	1	1	100.00
V2	alert_test	i2c_alert_test	1.440s	28.459us	1	1	100.00
V2	intr_test	i2c_intr_test	1.780s	51.671us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.550s	44.655us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.550s	44.655us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.740s	75.984us	1	1	100.00
		i2c_csr_rw	1.690s	57.694us	1	1	100.00
		i2c_csr_aliasing	1.920s	871.905us	1	1	100.00
		i2c_same_csr_outstanding	11.630s	6.283ms	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.740s	75.984us	1	1	100.00
		i2c_csr_rw	1.690s	57.694us	1	1	100.00
		i2c_csr_aliasing	1.920s	871.905us	1	1	100.00
		i2c_same_csr_outstanding	11.630s	6.283ms	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.880s	81.103us	1	1	100.00
		i2c_sec_cm	1.660s	137.680us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.880s	81.103us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	4.540s	185.693us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.110s	47.306us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	12.780s	3.877ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.107762875240466166913487104427100107187683247751613336325869637864725701192116
    Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 185692711 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 185692711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.53499511470976102286890907444849835001833048220135264372051448822455075863066
    Line 95, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3877378227 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3877378227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.108903203495444270478096157665317924210283691689189574524158531720615392035070
Line 299, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 18140205481 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4009700

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.42649381208142563654204771422028237809983487421072945127402984560349245592153
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  47305540 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 231 [0xe7])
  UVM_INFO @  47305540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.94750012405573407231905935172549708151829307046039207157795445610755639225053
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10147121264 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10147121264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```