KMAC/MASKED Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	10.430s	1.065ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.740s	40.050us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.910s	34.559us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.220s	1.456ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.850s	757.898us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.560s	116.327us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.910s	34.559us	1	1	100.00
		kmac_csr_aliasing	6.850s	757.898us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.780s	35.389us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.070s	35.573us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	37.322m	25.823ms	1	1	100.00
V2	burst_write	kmac_burst_write	13.967m	43.891ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.682m	365.735ms	1	1	100.00
		kmac_test_vectors_sha3_256	31.000s	4.725ms	1	1	100.00
		kmac_test_vectors_sha3_384	24.463m	365.201ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.910s	1.219ms	1	1	100.00
		kmac_test_vectors_shake_128	2.658m	8.711ms	1	1	100.00
		kmac_test_vectors_shake_256	1.588m	6.826ms	1	1	100.00
		kmac_test_vectors_kmac	3.050s	97.868us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.550s	653.906us	1	1	100.00
V2	sideload	kmac_sideload	2.466m	71.414ms	1	1	100.00
V2	app	kmac_app	3.413m	12.325ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.607m	4.289ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.131m	8.453ms	1	1	100.00
V2	error	kmac_error	1.729m	4.534ms	1	1	100.00
V2	key_error	kmac_key_error	10.670s	1.229ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.410s	75.576us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.830s	46.595us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.870s	34.476us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	17.440s	2.745ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	6.370s	770.385us	1	1	100.00
V2	stress_all	kmac_stress_all	16.615m	82.045ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.410s	68.396us	1	1	100.00
V2	alert_test	kmac_alert_test	1.930s	185.275us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.220s	125.326us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.220s	125.326us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.740s	40.050us	1	1	100.00
		kmac_csr_rw	1.910s	34.559us	1	1	100.00
		kmac_csr_aliasing	6.850s	757.898us	1	1	100.00
		kmac_same_csr_outstanding	2.100s	212.189us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.740s	40.050us	1	1	100.00
		kmac_csr_rw	1.910s	34.559us	1	1	100.00
		kmac_csr_aliasing	6.850s	757.898us	1	1	100.00
		kmac_same_csr_outstanding	2.100s	212.189us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.070s	128.733us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.070s	128.733us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.070s	128.733us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.070s	128.733us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.160s	44.335us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	33.800s	4.041ms	1	1	100.00
		kmac_tl_intg_err	2.690s	194.366us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.690s	194.366us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	6.370s	770.385us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	10.430s	1.065ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.466m	71.414ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.070s	128.733us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	33.800s	4.041ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	33.800s	4.041ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	33.800s	4.041ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	10.430s	1.065ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	6.370s	770.385us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	33.800s	4.041ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.420m	7.872ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	10.430s	1.065ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.934m	7.626ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.63673713606524711258352670481380892115369360561913503948161588471140035535660
      Line 237, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7626496379 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 7626496379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.62037875737692571935768791775082637295516709548761336594342496419376483543317
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
        UVM_ERROR @  44335301 ps: (kmac_csr_assert_fpv.sv:525) [ASSERT FAILED] prefix_6_rd_A
        UVM_INFO @  44335301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---