KMAC/UNMASKED Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	10.860s	889.152us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.850s	38.654us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.560s	25.198us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.800s	889.258us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.400s	199.711us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.420s	78.074us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.560s	25.198us	1	1	100.00
		kmac_csr_aliasing	4.400s	199.711us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.580s	157.653us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.170s	152.060us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	13.312m	43.511ms	1	1	100.00
V2	burst_write	kmac_burst_write	9.543m	57.782ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.020s	665.511us	1	1	100.00
		kmac_test_vectors_sha3_256	26.870s	10.006ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.288m	66.555ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.560s	754.101us	1	1	100.00
		kmac_test_vectors_shake_128	1.570m	4.702ms	1	1	100.00
		kmac_test_vectors_shake_256	22.290m	57.879ms	1	1	100.00
		kmac_test_vectors_kmac	3.070s	329.810us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.530s	82.765us	1	1	100.00
V2	sideload	kmac_sideload	33.110s	4.561ms	1	1	100.00
V2	app	kmac_app	2.159m	47.844ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.780m	9.637ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.182m	2.502ms	1	1	100.00
V2	error	kmac_error	49.930s	38.582ms	1	1	100.00
V2	key_error	kmac_key_error	2.800s	1.993ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.353m	10.008ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	6.340s	304.904us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	3.760s	199.250us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	33.290s	5.786ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.990s	340.847us	1	1	100.00
V2	stress_all	kmac_stress_all	9.236m	39.059ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.640s	19.850us	1	1	100.00
V2	alert_test	kmac_alert_test	1.720s	16.375us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.380s	60.996us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.380s	60.996us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.850s	38.654us	1	1	100.00
		kmac_csr_rw	1.560s	25.198us	1	1	100.00
		kmac_csr_aliasing	4.400s	199.711us	1	1	100.00
		kmac_same_csr_outstanding	2.440s	184.588us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.850s	38.654us	1	1	100.00
		kmac_csr_rw	1.560s	25.198us	1	1	100.00
		kmac_csr_aliasing	4.400s	199.711us	1	1	100.00
		kmac_same_csr_outstanding	2.440s	184.588us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.880s	64.575us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.880s	64.575us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.880s	64.575us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.880s	64.575us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.610s	40.458us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	45.940s	4.668ms	1	1	100.00
		kmac_tl_intg_err	1.610s	13.839us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.610s	13.839us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.990s	340.847us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	10.860s	889.152us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	33.110s	4.561ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.880s	64.575us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	45.940s	4.668ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	45.940s	4.668ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	45.940s	4.668ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	10.860s	889.152us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.990s	340.847us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	45.940s	4.668ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.761m	4.369ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	10.860s	889.152us	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	41.930s	4.368ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			37	40	92.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.32336304303265793957816416826436891775719428948917014562216585897133603172486
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
        UVM_ERROR @  40457543 ps: (kmac_csr_assert_fpv.sv:525) [ASSERT FAILED] prefix_6_rd_A
        UVM_INFO @  40457543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.15060996420236807252237079398579789585990323865317732808570822466362118923458
      Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
        UVM_ERROR @  13839189 ps: (kmac_csr_assert_fpv.sv:540) [ASSERT FAILED] prefix_9_rd_A
        UVM_INFO @  13839189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.87476628598177688776610403187562898259149527082309517034329739385837376643127
      Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10007918539 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9a2a5000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10007918539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---