OTBN Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 11.000s 147.030us 1 1 100.00
V1 single_binary otbn_single 11.000s 38.768us 1 1 100.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 24.585us 1 1 100.00
V1 csr_rw otbn_csr_rw 5.000s 75.211us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 7.000s 79.357us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 7.000s 25.694us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 7.000s 40.144us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 5.000s 75.211us 1 1 100.00
otbn_csr_aliasing 7.000s 25.694us 1 1 100.00
V1 mem_walk otbn_mem_walk 26.000s 2.441ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 11.000s 736.484us 1 1 100.00
V1 TOTAL 9 9 100.00
V2 reset_recovery otbn_reset 17.000s 226.010us 1 1 100.00
V2 multi_error otbn_multi_err 36.000s 1.099ms 1 1 100.00
V2 back_to_back otbn_multi 17.000s 191.050us 1 1 100.00
V2 stress_all otbn_stress_all 18.000s 75.408us 1 1 100.00
V2 lc_escalation otbn_escalate 11.000s 31.125us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 7.000s 21.809us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 9.000s 40.532us 1 1 100.00
V2 alert_test otbn_alert_test 6.000s 66.561us 1 1 100.00
V2 intr_test otbn_intr_test 5.000s 47.279us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 6.000s 344.824us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 6.000s 344.824us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 24.585us 1 1 100.00
otbn_csr_rw 5.000s 75.211us 1 1 100.00
otbn_csr_aliasing 7.000s 25.694us 1 1 100.00
otbn_same_csr_outstanding 7.000s 27.553us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 24.585us 1 1 100.00
otbn_csr_rw 5.000s 75.211us 1 1 100.00
otbn_csr_aliasing 7.000s 25.694us 1 1 100.00
otbn_same_csr_outstanding 7.000s 27.553us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S mem_integrity otbn_imem_err 8.000s 18.471us 1 1 100.00
otbn_dmem_err 9.000s 16.766us 1 1 100.00
V2S internal_integrity otbn_alu_bignum_mod_err 7.000s 12.205us 1 1 100.00
otbn_controller_ispr_rdata_err 10.000s 54.610us 1 1 100.00
otbn_mac_bignum_acc_err 10.000s 27.042us 1 1 100.00
otbn_urnd_err 7.000s 45.222us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 41.907us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 9.000s 21.632us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 8.000s 27.088us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 3.117m 1.245ms 1 1 100.00
otbn_tl_intg_err 11.000s 270.840us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 51.000s 329.781us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 3.117m 1.245ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 3.117m 1.245ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 11.000s 147.030us 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 9.000s 16.766us 1 1 100.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 8.000s 18.471us 1 1 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 11.000s 270.840us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 11.000s 31.125us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 8.000s 18.471us 1 1 100.00
otbn_dmem_err 9.000s 16.766us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 21.809us 1 1 100.00
otbn_illegal_mem_acc 8.000s 41.907us 1 1 100.00
otbn_sec_cm 3.117m 1.245ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 3.117m 1.245ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 11.000s 38.768us 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 8.000s 18.471us 1 1 100.00
otbn_dmem_err 9.000s 16.766us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 21.809us 1 1 100.00
otbn_illegal_mem_acc 8.000s 41.907us 1 1 100.00
otbn_sec_cm 3.117m 1.245ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 3.117m 1.245ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 11.000s 31.125us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 8.000s 18.471us 1 1 100.00
otbn_dmem_err 9.000s 16.766us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 21.809us 1 1 100.00
otbn_illegal_mem_acc 8.000s 41.907us 1 1 100.00
otbn_sec_cm 3.117m 1.245ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 3.117m 1.245ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 11.000s 38.768us 1 1 100.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 7.000s 92.561us 1 1 100.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 7.000s 13.058us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 20.000s 89.948us 1 1 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 20.000s 89.948us 1 1 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 11.000s 42.347us 1 1 100.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 3.117m 1.245ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 3.117m 1.245ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 8.000s 215.666us 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 3.117m 1.245ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 3.117m 1.245ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 11.000s 634.617us 1 1 100.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 11.000s 634.617us 1 1 100.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 7.000s 23.424us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 11.000s 38.768us 1 1 100.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 11.000s 38.768us 1 1 100.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 11.000s 38.768us 1 1 100.00
V2S sec_cm_write_mem_integrity otbn_multi 17.000s 191.050us 1 1 100.00
V2S sec_cm_ctrl_flow_count otbn_single 11.000s 38.768us 1 1 100.00
V2S sec_cm_ctrl_flow_sca otbn_single 11.000s 38.768us 1 1 100.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 8.000s 62.910us 1 1 100.00
V2S sec_cm_key_sideload otbn_single 11.000s 38.768us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 3.117m 1.245ms 1 1 100.00
V2S TOTAL 20 20 100.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 51.000s 770.793us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 41 41 100.00