PATTGEN Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	128.928us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	29.275us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	13.532us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	739.835us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	13.076us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	39.957us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	13.532us	1	1	100.00
		pattgen_csr_aliasing	4.000s	13.076us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	13.000s	1.373ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	21.000s	2.718ms	1	1	100.00
V2	error	pattgen_error	4.000s	112.770us	1	1	100.00
V2	stress_all	pattgen_stress_all			0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	41.044us	1	1	100.00
V2	intr_test	pattgen_intr_test	3.000s	14.589us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	4.000s	64.362us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	4.000s	64.362us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	29.275us	1	1	100.00
		pattgen_csr_rw	4.000s	13.532us	1	1	100.00
		pattgen_csr_aliasing	4.000s	13.076us	1	1	100.00
		pattgen_same_csr_outstanding	3.000s	211.875us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	29.275us	1	1	100.00
		pattgen_csr_rw	4.000s	13.532us	1	1	100.00
		pattgen_csr_aliasing	4.000s	13.076us	1	1	100.00
		pattgen_same_csr_outstanding	3.000s	211.875us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	513.549us	1	1	100.00
		pattgen_sec_cm	4.000s	72.986us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	513.549us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	1.250m	12.363ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	4.000s	94.225us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.13410117909744293677199775679443576244690967582312701659487041730948812917684
      Line 122, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3673792919 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 3673794464 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3673794464 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @ 3673994464 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• Job timed out after * minutes has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.7350433477204944266143248898439887854453679970497884513178779307207388238134
      Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        Job timed out after 180 minutes