ROM_CTRL/32KB Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.700s 2.128ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.120s 306.554us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.000s 536.132us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.870s 327.072us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.370s 995.439us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.630s 445.268us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.000s 536.132us 1 1 100.00
rom_ctrl_csr_aliasing 4.370s 995.439us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.860s 169.493us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.730s 291.448us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.090s 172.019us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 13.060s 4.996ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.000s 2.026ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.140s 127.315us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.530s 1.422ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.530s 1.422ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.120s 306.554us 1 1 100.00
rom_ctrl_csr_rw 6.000s 536.132us 1 1 100.00
rom_ctrl_csr_aliasing 4.370s 995.439us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.020s 2.005ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.120s 306.554us 1 1 100.00
rom_ctrl_csr_rw 6.000s 536.132us 1 1 100.00
rom_ctrl_csr_aliasing 4.370s 995.439us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.020s 2.005ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.081m 8.098ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 22.780s 1.704ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.480m 652.381us 1 1 100.00
rom_ctrl_tl_intg_err 45.380s 602.909us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.480m 652.381us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.480m 652.381us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.081m 8.098ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.081m 8.098ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.081m 8.098ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.081m 8.098ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.081m 8.098ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.480m 652.381us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.480m 652.381us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.700s 2.128ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.700s 2.128ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.700s 2.128ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 45.380s 602.909us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.081m 8.098ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.000s 2.026ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.081m 8.098ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.081m 8.098ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.081m 8.098ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 22.780s 1.704ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.480m 652.381us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 6.814m 9.057ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00