RV_DM/USE_JTAG_INTERFACE Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.960s 1.021ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.700s 124.665us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.660s 481.814us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 17.530s 13.872ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.880s 463.372us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 5.790s 4.014ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 3.110s 1.633ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 19.370s 9.657ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 32.710s 58.022ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.960s 315.504us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 2.120s 379.687us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.620s 216.981us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.930s 824.569us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.680s 102.921us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.530s 1.003ms 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.690s 69.900us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.050s 731.693us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.960s 315.504us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.970s 275.288us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.770s 417.409us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.620s 216.981us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.690s 69.386us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.120s 60.930us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.150s 309.900us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 52.890s 11.953ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 41.420s 2.348ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.560s 17.935us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 41.420s 2.348ms 1 1 100.00
rv_dm_csr_rw 2.150s 309.900us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.590s 111.947us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.730s 156.831us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 1.960s 1.021ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.810s 603.411us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.200s 305.578us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.770s 115.164us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.780s 381.941us 1 1 100.00
V2 sba rv_dm_sba_tl_access 3.000s 1.542ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.680s 250.261us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 4.560s 4.205ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.580s 83.724us 0 1 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.750s 248.123us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.450s 1.540ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.760s 151.937us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.700s 109.295us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 6.650s 6.881ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.780s 23.925us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.520s 109.946us 1 1 100.00
V2 stress_all rv_dm_stress_all 5.910s 6.434ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.650s 52.228us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.570s 14.770us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.570s 14.770us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 41.420s 2.348ms 1 1 100.00
rv_dm_csr_hw_reset 2.120s 60.930us 1 1 100.00
rv_dm_csr_rw 2.150s 309.900us 1 1 100.00
rv_dm_same_csr_outstanding 5.390s 577.962us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 41.420s 2.348ms 1 1 100.00
rv_dm_csr_hw_reset 2.120s 60.930us 1 1 100.00
rv_dm_csr_rw 2.150s 309.900us 1 1 100.00
rv_dm_same_csr_outstanding 5.390s 577.962us 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 1.890s 600.835us 1 1 100.00
rv_dm_tl_intg_err 8.530s 866.377us 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 8.530s 866.377us 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.450s 1.540ms 1 1 100.00
rv_dm_debug_disabled 1.840s 39.122us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.450s 1.540ms 1 1 100.00
rv_dm_debug_disabled 1.840s 39.122us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 1.960s 1.021ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.640s 158.904us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.600s 53.049us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.600s 53.049us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.640s 158.904us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 2.280s 50.745us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.510s 54.872us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets