RV_TIMER Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.510s	34.523us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.480s	13.821us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.670s	180.698us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.870s	275.441us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.870s	41.399us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.610s	111.130us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.670s	180.698us	1	1	100.00
		rv_timer_csr_aliasing	1.870s	41.399us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	6.690s	15.790ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.930s	902.253us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.796m	250.143ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.796m	250.143ms	1	1	100.00
V2	stress	rv_timer_stress_all	4.100s	15.422ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.610s	61.199us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.570s	16.275us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.910s	54.591us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.910s	54.591us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.480s	13.821us	1	1	100.00
		rv_timer_csr_rw	1.670s	180.698us	1	1	100.00
		rv_timer_csr_aliasing	1.870s	41.399us	1	1	100.00
		rv_timer_same_csr_outstanding	1.490s	67.510us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.480s	13.821us	1	1	100.00
		rv_timer_csr_rw	1.670s	180.698us	1	1	100.00
		rv_timer_csr_aliasing	1.870s	41.399us	1	1	100.00
		rv_timer_same_csr_outstanding	1.490s	67.510us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.110s	92.090us	1	1	100.00
		rv_timer_tl_intg_err	2.070s	274.358us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.070s	274.358us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	17.100s	5.019ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.450s	27.280us	1	1	100.00
		rv_timer_max	1.490s	29.000us	1	1	100.00
		TOTAL			19	19	100.00