SPI_DEVICE/1R1W Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	3.778m	123.404ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.140s	106.693us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.870s	92.003us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.140s	5.013ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.710s	323.893us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.980s	332.301us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.870s	92.003us	1	1	100.00
		spi_device_csr_aliasing	6.710s	323.893us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.710s	21.815us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.590s	62.741us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	2.090s	17.867us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.580s	5.075us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.590s	7.352us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.980s	141.492us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.980s	141.492us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	13.550s	5.696ms	1	1	100.00
		spi_device_tpm_sts_read	1.940s	52.003us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	20.690s	5.396ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	18.010s	8.891ms	1	1	100.00
		spi_device_flash_all	1.123m	8.253ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.480s	266.266us	1	1	100.00
		spi_device_flash_all	1.123m	8.253ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.480s	266.266us	1	1	100.00
		spi_device_flash_all	1.123m	8.253ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.123m	8.253ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.670s	502.701us	1	1	100.00
		spi_device_flash_all	1.123m	8.253ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.670s	502.701us	1	1	100.00
		spi_device_flash_all	1.123m	8.253ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.670s	502.701us	1	1	100.00
		spi_device_flash_all	1.123m	8.253ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.670s	502.701us	1	1	100.00
		spi_device_flash_all	1.123m	8.253ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.670s	502.701us	1	1	100.00
		spi_device_flash_all	1.123m	8.253ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	18.970s	24.235ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	4.260s	844.726us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.260s	844.726us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.260s	844.726us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.850s	395.170us	1	1	100.00
		spi_device_read_buffer_direct	4.000s	894.342us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.260s	844.726us	1	1	100.00
		spi_device_flash_all	1.123m	8.253ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.123m	8.253ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.123m	8.253ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	8.920s	783.348us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	8.920s	783.348us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	3.778m	123.404ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	4.800s	659.963us	1	1	100.00
V2	stress_all	spi_device_stress_all	2.060s	137.538us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.940s	41.957us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.720s	92.610us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.150s	759.522us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.150s	759.522us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.140s	106.693us	1	1	100.00
		spi_device_csr_rw	2.870s	92.003us	1	1	100.00
		spi_device_csr_aliasing	6.710s	323.893us	1	1	100.00
		spi_device_same_csr_outstanding	2.830s	63.365us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.140s	106.693us	1	1	100.00
		spi_device_csr_rw	2.870s	92.003us	1	1	100.00
		spi_device_csr_aliasing	6.710s	323.893us	1	1	100.00
		spi_device_same_csr_outstanding	2.830s	63.365us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.870s	211.844us	1	1	100.00
		spi_device_tl_intg_err	6.170s	103.175us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.170s	103.175us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	35.900s	27.198ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.43081679538564349083261921961889538771109571676670437506639393435435859017531
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3756488 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[20])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3756488 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3756488 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[916])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.29426587284705014932020775641032553530849560286799610545596284142833528363578
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4632063 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xab0ea4 [101010110000111010100100] vs 0x0 [0])
        UVM_ERROR @   4633063 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x790b6 [1111001000010110110] vs 0x0 [0])
        UVM_ERROR @   4679063 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdf9705 [110111111001011100000101] vs 0x0 [0])
        UVM_ERROR @   4729063 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfe6356 [111111100110001101010110] vs 0x0 [0])
        UVM_ERROR @   4821063 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa1cf15 [101000011100111100010101] vs 0x0 [0])