SPI_DEVICE/2P Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	35.060s	10.071ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.230s	43.139us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.220s	241.628us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.320s	2.407ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.810s	5.843ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.320s	351.334us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.220s	241.628us	1	1	100.00
		spi_device_csr_aliasing	17.810s	5.843ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.470s	13.665us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.550s	67.328us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.820s	19.766us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.840s	44.541us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.900s	18.504us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.570s	10.685us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.570s	10.685us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	10.060s	3.482ms	1	1	100.00
		spi_device_tpm_sts_read	1.730s	395.315us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	19.410s	12.016ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	9.910s	1.888ms	1	1	100.00
		spi_device_flash_all	44.120s	21.113ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.590s	13.142ms	1	1	100.00
		spi_device_flash_all	44.120s	21.113ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.590s	13.142ms	1	1	100.00
		spi_device_flash_all	44.120s	21.113ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	44.120s	21.113ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	7.000s	4.188ms	1	1	100.00
		spi_device_flash_all	44.120s	21.113ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	7.000s	4.188ms	1	1	100.00
		spi_device_flash_all	44.120s	21.113ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	7.000s	4.188ms	1	1	100.00
		spi_device_flash_all	44.120s	21.113ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	7.000s	4.188ms	1	1	100.00
		spi_device_flash_all	44.120s	21.113ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	7.000s	4.188ms	1	1	100.00
		spi_device_flash_all	44.120s	21.113ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	24.020s	43.652ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	3.420s	69.609us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.420s	69.609us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.420s	69.609us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.870s	2.191ms	1	1	100.00
		spi_device_read_buffer_direct	4.010s	790.153us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.420s	69.609us	1	1	100.00
		spi_device_flash_all	44.120s	21.113ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	44.120s	21.113ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	44.120s	21.113ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.210s	137.936us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.210s	137.936us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	35.060s	10.071ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	41.200s	63.420ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.640s	269.397us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.600s	23.785us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.580s	47.403us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.780s	95.827us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.780s	95.827us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.230s	43.139us	1	1	100.00
		spi_device_csr_rw	3.220s	241.628us	1	1	100.00
		spi_device_csr_aliasing	17.810s	5.843ms	1	1	100.00
		spi_device_same_csr_outstanding	3.140s	126.653us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.230s	43.139us	1	1	100.00
		spi_device_csr_rw	3.220s	241.628us	1	1	100.00
		spi_device_csr_aliasing	17.810s	5.843ms	1	1	100.00
		spi_device_same_csr_outstanding	3.140s	126.653us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.080s	93.438us	1	1	100.00
		spi_device_tl_intg_err	9.800s	7.642ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.800s	7.642ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.065m	23.552ms	1	1	100.00
		TOTAL			33	33	100.00