SRAM_CTRL/MAIN Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 12.470s 1.046ms 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.750s 21.339us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 1.550s 13.838us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.360s 60.759us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.660s 16.326us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.040s 360.956us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.550s 13.838us 1 1 100.00
sram_ctrl_csr_aliasing 1.660s 16.326us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 3.805m 13.829ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 1.724m 5.026ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 2.620m 4.424ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 3.824m 5.615ms 1 1 100.00
V2 bijection sram_ctrl_bijection 32.050m 550.430ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 7.215m 208.535ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.572m 62.624ms 1 1 100.00
V2 executable sram_ctrl_executable 6.594m 50.979ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 15.070s 953.995us 1 1 100.00
sram_ctrl_partial_access_b2b 4.831m 66.021ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 35.090s 1.514ms 1 1 100.00
sram_ctrl_throughput_w_partial_write 24.570s 745.526us 1 1 100.00
sram_ctrl_throughput_w_readback 1.142m 2.940ms 1 1 100.00
V2 regwen sram_ctrl_regwen 12.386m 20.458ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 3.320s 699.806us 1 1 100.00
V2 stress_all sram_ctrl_stress_all 1.098h 430.201ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 1.890s 48.091us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.900s 141.389us 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.900s 141.389us 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.750s 21.339us 1 1 100.00
sram_ctrl_csr_rw 1.550s 13.838us 1 1 100.00
sram_ctrl_csr_aliasing 1.660s 16.326us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.680s 16.429us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.750s 21.339us 1 1 100.00
sram_ctrl_csr_rw 1.550s 13.838us 1 1 100.00
sram_ctrl_csr_aliasing 1.660s 16.326us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.680s 16.429us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 18.160s 7.381ms 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 1.780s 3.399us 0 1 0.00
sram_ctrl_tl_intg_err 2.900s 187.915us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 1.780s 3.399us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.900s 187.915us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 12.386m 20.458ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 12.386m 20.458ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.550s 13.838us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 6.594m 50.979ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 6.594m 50.979ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 6.594m 50.979ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.572m 62.624ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 4.360s 685.559us 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 18.160s 7.381ms 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 8.140s 2.650ms 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 12.470s 1.046ms 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 12.470s 1.046ms 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 6.594m 50.979ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 1.780s 3.399us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.572m 62.624ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 1.780s 3.399us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 1.780s 3.399us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 12.470s 1.046ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 1.780s 3.399us 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 21.840s 4.229ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets