SRAM_CTRL/RET Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.800s	500.333us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.620s	50.515us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.950s	15.249us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.080s	242.323us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.570s	42.909us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.760s	83.839us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.950s	15.249us	1	1	100.00
		sram_ctrl_csr_aliasing	1.570s	42.909us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	9.230s	684.978us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.270s	325.424us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.792m	32.023ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.953m	1.796ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	32.810s	2.555ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	12.041m	42.507ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.020s	491.909us	1	1	100.00
V2	executable	sram_ctrl_executable	11.038m	9.528ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	8.660s	498.514us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.482m	33.528ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.230s	185.319us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	12.260s	539.008us	1	1	100.00
		sram_ctrl_throughput_w_readback	54.150s	1.171ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	2.548m	14.858ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.140s	27.793us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	43.982m	248.801ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.740s	13.303us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.900s	59.082us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.900s	59.082us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.620s	50.515us	1	1	100.00
		sram_ctrl_csr_rw	1.950s	15.249us	1	1	100.00
		sram_ctrl_csr_aliasing	1.570s	42.909us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.480s	21.797us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.620s	50.515us	1	1	100.00
		sram_ctrl_csr_rw	1.950s	15.249us	1	1	100.00
		sram_ctrl_csr_aliasing	1.570s	42.909us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.480s	21.797us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.670s	1.426ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.520s	3.604us	0	1	0.00
		sram_ctrl_tl_intg_err	2.510s	1.786ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.520s	3.604us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.510s	1.786ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	2.548m	14.858ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	2.548m	14.858ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.950s	15.249us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	11.038m	9.528ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	11.038m	9.528ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	11.038m	9.528ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.020s	491.909us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.650s	33.344us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.670s	1.426ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.700s	49.977us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.800s	500.333us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.800s	500.333us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	11.038m	9.528ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.520s	3.604us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.020s	491.909us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.520s	3.604us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.520s	3.604us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.800s	500.333us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.520s	3.604us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.127m	4.988ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.78376393389179858421773301992186799387371419074418882214787625866330474830424
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  49977341 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x59) != exp (0x4a)
        UVM_INFO @  49977341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.43008298926230554702482589312182222403378421536809847537037409301975491703304
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3604099 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3604099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---