SYSRST_CTRL Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	3.520s	2.121ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	6.620s	2.457ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	3.670s	2.437ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	2.290s	2.371ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	4.990s	4.031ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	3.000s	2.056ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	15.700s	38.655ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	2.710s	2.678ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	2.320s	2.224ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	3.000s	2.056ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	2.710s	2.678ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	47.360s	81.469ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	14.270s	29.328ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	3.020s	3.028ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	3.140s	4.818ms	0	1	0.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	2.430s	2.535ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	2.960s	2.050ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	7.420s	3.184ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.640s	2.634ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.670s	7.029ms	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	17.670s	36.101ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	29.160s	14.170ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	5.400s	2.010ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	2.450s	2.038ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	5.630s	2.027ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	5.630s	2.027ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	4.990s	4.031ms	1	1	100.00
		sysrst_ctrl_csr_rw	3.000s	2.056ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	2.710s	2.678ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	26.470s	10.087ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	4.990s	4.031ms	1	1	100.00
		sysrst_ctrl_csr_rw	3.000s	2.056ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	2.710s	2.678ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	26.470s	10.087ms	1	1	100.00
V2		TOTAL			13	15	86.67
V2S	tl_intg_err	sysrst_ctrl_sec_cm	9.500s	22.117ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	1.446m	42.453ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.446m	42.453ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	4.740s	17.270ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 2 failures:

  • Test sysrst_ctrl_ultra_low_pwr has 1 failures.

    • 0.sysrst_ctrl_ultra_low_pwr.115775891544766030743993644714352044828463678701812373013049248524304854913770
      Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

        UVM_ERROR @ 7028811782 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 7028948146 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 7028948146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test sysrst_ctrl_edge_detect has 1 failures.

    • 0.sysrst_ctrl_edge_detect.77385728388280061571854698339383403081237603528383206898542201237052184357864
      Line 389, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest/run.log

        UVM_ERROR @ 4818318276 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 4818443276 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 4818443276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---