UART Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	22.440s	5.913ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.520s	27.744us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.920s	14.112us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.560s	121.363us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.830s	57.507us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.500s	34.534us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.920s	14.112us	1	1	100.00
		uart_csr_aliasing	1.830s	57.507us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	3.560s	4.817ms	1	1	100.00
V2	parity	uart_smoke	22.440s	5.913ms	1	1	100.00
		uart_tx_rx	3.560s	4.817ms	1	1	100.00
V2	parity_error	uart_intr	17.550s	29.770ms	1	1	100.00
		uart_rx_parity_err	29.790s	21.626ms	1	1	100.00
V2	watermark	uart_tx_rx	3.560s	4.817ms	1	1	100.00
		uart_intr	17.550s	29.770ms	1	1	100.00
V2	fifo_full	uart_fifo_full	48.180s	360.082ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	4.533m	176.617ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	22.150s	59.577ms	1	1	100.00
V2	rx_frame_err	uart_intr	17.550s	29.770ms	1	1	100.00
V2	rx_break_err	uart_intr	17.550s	29.770ms	1	1	100.00
V2	rx_timeout	uart_intr	17.550s	29.770ms	1	1	100.00
V2	perf	uart_perf	7.082m	14.381ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.180s	7.988ms	1	1	100.00
V2	line_loopback	uart_loopback	5.180s	7.988ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.256m	46.141ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.680s	746.289us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	32.230s	6.707ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	20.810s	3.998ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.639m	160.218ms	1	1	100.00
V2	stress_all	uart_stress_all	1.167m	68.159ms	1	1	100.00
V2	alert_test	uart_alert_test	1.530s	37.775us	1	1	100.00
V2	intr_test	uart_intr_test	1.560s	17.295us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.620s	140.343us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.620s	140.343us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.520s	27.744us	1	1	100.00
		uart_csr_rw	1.920s	14.112us	1	1	100.00
		uart_csr_aliasing	1.830s	57.507us	1	1	100.00
		uart_same_csr_outstanding	1.450s	32.662us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.520s	27.744us	1	1	100.00
		uart_csr_rw	1.920s	14.112us	1	1	100.00
		uart_csr_aliasing	1.830s	57.507us	1	1	100.00
		uart_same_csr_outstanding	1.450s	32.662us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	2.070s	121.771us	1	1	100.00
		uart_tl_intg_err	1.980s	180.732us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.980s	180.732us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	5.970s	2.181ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00