CHIP Simulation Results

Monday May 19 2025 20:17:11 UTC

GitHub Revision: `b21d4d7`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.483m	2.149ms	1	1	100.00
		chip_sw_example_rom	1.129m	2.238ms	1	1	100.00
		chip_sw_example_manufacturer	1.791m	2.629ms	1	1	100.00
		chip_sw_example_concurrency	2.907m	2.796ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.430m	7.848ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.987m	4.122ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	4.499m	6.000ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	48.431m	28.096ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	45.460s	2.408ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	48.431m	28.096ms	1	1	100.00
		chip_csr_rw	2.987m	4.122ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.010s	42.770us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.041m	4.271ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.041m	4.271ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.041m	4.271ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.821m	4.518ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.821m	4.518ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.459m	4.052ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	4.657m	3.599ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.437m	3.972ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	4.303m	4.054ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.530m	4.157ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.211m	3.732ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	3.288m	5.579ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.288m	5.579ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.637m	2.777ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.595m	2.797ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.591m	4.588ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	16.123m	15.341ms	1	1	100.00
		chip_tap_straps_testunlock0	7.001m	6.657ms	1	1	100.00
		chip_tap_straps_rma	3.591m	4.184ms	1	1	100.00
		chip_tap_straps_prod	1.954m	2.987ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.025m	3.099ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.938m	9.932ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.843m	5.008ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.843m	5.008ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.308m	8.089ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	26.879m	18.642ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.300m	4.141ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.232m	6.725ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	50.346m	18.250ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.304m	3.031ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.909m	7.716ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.910m	2.983ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.987m	7.561ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.754m	3.377ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.195m	5.202ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.239m	3.030ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.430m	3.489ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.446m	5.773ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.567m	5.611ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.345m	2.824ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.567m	5.611ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.998m	2.850ms	1	1	100.00
		chip_sw_aes_smoketest	2.613m	2.584ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.864m	2.432ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.596m	2.789ms	1	1	100.00
		chip_sw_csrng_smoketest	2.014m	3.267ms	1	1	100.00
		chip_sw_entropy_src_smoketest	5.162m	3.347ms	1	1	100.00
		chip_sw_gpio_smoketest	2.873m	2.886ms	1	1	100.00
		chip_sw_hmac_smoketest	2.774m	2.859ms	1	1	100.00
		chip_sw_kmac_smoketest	2.773m	3.108ms	1	1	100.00
		chip_sw_otbn_smoketest	17.575m	10.976ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.218m	6.279ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.842m	4.834ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.419m	3.129ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.244m	2.953ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.435m	3.080ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.629m	2.515ms	1	1	100.00
		chip_sw_uart_smoketest	2.143m	3.253ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.998m	3.004ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.380m	3.857ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.956h	60.947ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	35.620m	14.977ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	23.839s		0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.155m	2.811ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.190m	3.486ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.700h	53.783ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.871h	57.040ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	46.560s	2.094ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	46.560s	2.094ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	48.431m	28.096ms	1	1	100.00
		chip_same_csr_outstanding	20.160m	16.730ms	1	1	100.00
		chip_csr_hw_reset	3.430m	7.848ms	1	1	100.00
		chip_csr_rw	2.987m	4.122ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	48.431m	28.096ms	1	1	100.00
		chip_same_csr_outstanding	20.160m	16.730ms	1	1	100.00
		chip_csr_hw_reset	3.430m	7.848ms	1	1	100.00
		chip_csr_rw	2.987m	4.122ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	25.700s	431.937us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.230s	52.431us	1	1	100.00
		xbar_smoke_large_delays	36.460s	5.982ms	1	1	100.00
		xbar_smoke_slow_rsp	32.970s	3.852ms	1	1	100.00
		xbar_random_zero_delays	7.510s	87.248us	1	1	100.00
		xbar_random_large_delays	37.570s	6.212ms	1	1	100.00
		xbar_random_slow_rsp	2.278m	16.348ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	26.230s	970.349us	1	1	100.00
		xbar_error_and_unmapped_addr	5.290s	76.886us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	33.660s	1.295ms	1	1	100.00
		xbar_error_and_unmapped_addr	5.290s	76.886us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	7.210s	217.616us	1	1	100.00
		xbar_access_same_device_slow_rsp	1.700m	12.087ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	17.780s	951.816us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.846m	12.069ms	1	1	100.00
		xbar_stress_all_with_error	3.348m	11.074ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.659m	336.578us	1	1	100.00
		xbar_stress_all_with_reset_error	1.289m	326.880us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	35.620m	14.977ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	33.266m	28.764ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	34.159m	14.525ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.871s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.143s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	14.737s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.891s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	15.369s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	15.217s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	15.799s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	13.553s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	14.907s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	14.909s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	13.112s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.115s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	13.974s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	13.641s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	13.637s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	14.241s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	13.059s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	16.026s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.591s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	14.427s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.685s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.755s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.465s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.979s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.488s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.360s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.297s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.458s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13.071s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.815s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.996s		0	1	0.00
		rom_e2e_asm_init_dev	12.943s		0	1	0.00
		rom_e2e_asm_init_prod	13.097s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.880s		0	1	0.00
		rom_e2e_asm_init_rma	14.381s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.367m	15.447ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	34.614m	15.067ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	34.468m	15.487ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	35.643m	15.384ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.744m	34.547ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.744m	34.547ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.717m	2.639ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.304m	3.031ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.527m	3.131ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.144m	3.394ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	18.884m	11.053ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	1.890m	2.141ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.156m	4.596ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.356m	5.951ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.008m	5.234ms	1	1	100.00
		chip_plic_all_irqs_10	4.413m	3.472ms	1	1	100.00
		chip_plic_all_irqs_20	6.265m	4.788ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.031m	3.744ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.680m	13.050ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.548m	4.998ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.189m	2.674ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.521m	12.927ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.760m	7.997ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	17.461m	8.632ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.444m	7.754ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.191h	255.073ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.564m	4.193ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.218m	6.279ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.564m	4.193ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.296m	6.942ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.296m	6.942ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.516m	7.296ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.930m	4.206ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.391m	5.674ms	1	1	100.00
		chip_sw_aes_idle	2.144m	3.394ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.374m	3.642ms	1	1	100.00
		chip_sw_kmac_idle	2.317m	2.513ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.850m	4.720ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.254m	3.631ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.337m	3.953ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.571m	5.094ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.213m	11.366ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.171m	3.976ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.666m	4.115ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.518m	4.666ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.704m	4.873ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.445m	4.298ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.515m	4.606ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.308m	8.089ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.981m	6.168ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.518m	4.666ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.704m	4.873ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.300m	4.141ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.232m	6.725ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	50.346m	18.250ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.304m	3.031ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.909m	7.716ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.910m	2.983ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.987m	7.561ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.754m	3.377ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.195m	5.202ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.239m	3.030ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.819m	3.034ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.835m	4.665ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.792m	7.330ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	46.981m	23.763ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	3.185m	3.206ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.884m	3.591ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	10.999m	7.211ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.206m	3.677ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.805m	3.934ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	16.377m	22.693ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.129h	102.762ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.308m	8.089ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.136m	5.063ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.215m	3.183ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.356m	5.951ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.760m	7.997ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.182m	6.326ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.964m	2.854ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.000m	6.489ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.028m	3.158ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	26.736m	10.257ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.589m	2.718ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.928m	7.797ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.589m	2.718ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.182m	6.326ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.567m	3.161ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	15.406m	17.974ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.473m	5.653ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.232m	6.725ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.058m	4.112ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.300m	4.141ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	53.835m	43.544ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	15.406m	17.974ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.992m	3.310ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	25.652m	11.580ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.480m	3.994ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	53.835m	43.544ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.480m	3.994ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.480m	3.994ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.480m	3.994ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.480m	3.994ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.356m	5.951ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.666m	12.924ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.673m	4.987ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.089m	6.210ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.089m	6.210ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.076m	3.211ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.910m	2.983ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.374m	3.642ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.019m	2.524ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	15.339m	8.290ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.709m	4.638ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.173m	4.946ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.002m	5.373ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.589m	3.421ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	25.652m	11.580ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.987m	7.561ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	13.578m	7.364ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	18.884m	11.053ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	39.841m	16.521ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.615m	2.450ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.731m	2.854ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.754m	3.377ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	25.652m	11.580ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.233m	6.664ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.827m	2.636ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	9.933m	5.973ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.317m	2.513ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.156m	4.596ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	16.123m	15.341ms	1	1	100.00
		chip_tap_straps_rma	3.591m	4.184ms	1	1	100.00
		chip_tap_straps_prod	1.954m	2.987ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.011m	3.743ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.233m	6.664ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.233m	6.664ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.233m	6.664ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	14.356m	7.927ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.480m	3.994ms	1	1	100.00
		chip_sw_flash_rma_unlocked	53.835m	43.544ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.240m	2.971ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.257m	7.844ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.085m	6.167ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	10.016m	7.332ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.233m	6.664ms	1	1	100.00
		chip_sw_keymgr_key_derivation	25.652m	11.580ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.155m	9.052ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.112m	8.843ms	1	1	100.00
		chip_prim_tl_access	4.666m	12.924ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.981m	6.168ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.171m	3.976ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.666m	4.115ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.518m	4.666ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.704m	4.873ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.445m	4.298ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.515m	4.606ms	1	1	100.00
		chip_tap_straps_dev	16.123m	15.341ms	1	1	100.00
		chip_tap_straps_rma	3.591m	4.184ms	1	1	100.00
		chip_tap_straps_prod	1.954m	2.987ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.657m	14.870ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.716m	3.875ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.689m	3.842ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.589m	3.433ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.408m	3.422ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.919m	33.713ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.657m	14.870ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.004h	47.598ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.037h	50.694ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.632m	9.733ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	54.921m	45.779ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	21.919m	33.713ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.365m	2.376ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.118m	2.483ms	1	1	100.00
		rom_volatile_raw_unlock	19.879s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	49.270m	16.606ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	50.346m	18.250ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.391m	5.674ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.391m	5.674ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.391m	5.674ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.247m	3.271ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.233m	6.664ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	15.406m	17.974ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.247m	3.271ms	1	1	100.00
		chip_sw_keymgr_key_derivation	25.652m	11.580ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.109m	5.126ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.070m	2.720ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	15.406m	17.974ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.247m	3.271ms	1	1	100.00
		chip_sw_keymgr_key_derivation	25.652m	11.580ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.109m	5.126ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.070m	2.720ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.233m	6.664ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.744m	3.544ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.011m	3.743ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.240m	2.971ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.257m	7.844ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.085m	6.167ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	10.016m	7.332ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.233m	6.664ms	1	1	100.00
		chip_prim_tl_access	4.666m	12.924ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.666m	12.924ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.454m	8.350ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.079m	9.220ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	13.543m	21.892ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.683m	7.233ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.873m	8.103ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.290m	6.352ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	18.987m	27.025ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	10.280m	13.808ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.296m	6.942ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.993m	11.466ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.085m	3.571ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.079m	9.220ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.727m	3.907ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	28.062m	36.075ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.466m	7.157ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.298m	5.800ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.819m	22.865ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.216m	7.776ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.393m	8.564ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	21.197m	26.089ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.502m	3.282ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.356m	5.951ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.155m	9.052ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.155m	9.052ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.393m	8.564ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.819m	22.865ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.085m	3.571ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.218m	6.279ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.722m	4.308ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.316m	4.325ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.371m	3.657ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.680m	13.050ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.354m	3.349ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.356m	5.951ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	17.461m	8.632ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.148m	5.105ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.017m	4.703ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.462m	2.597ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.070m	2.720ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.316m	4.325ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.316m	4.325ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	12.110m	10.693ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.203m	13.770ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.722m	4.308ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.750m	5.865ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.904m	6.286ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.591m	4.184ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.657m	14.870ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.008m	5.234ms	1	1	100.00
		chip_plic_all_irqs_10	4.413m	3.472ms	1	1	100.00
		chip_plic_all_irqs_20	6.265m	4.788ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.480m	2.943ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.395m	2.868ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	35.620m	14.977ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.170m	8.383ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.626m	3.213ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.025m	3.241ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.173m	2.753ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.109m	5.126ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.195m	5.202ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.092m	7.633ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.496m	6.924ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.112m	8.843ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.356m	5.951ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.843m	5.008ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.216m	7.776ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	15.095m	23.017ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.453m	2.392ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.419m	3.675ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.125m	3.844ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.095m	23.017ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.095m	23.017ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	12.121m	11.927ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	12.121m	11.927ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.487m	4.988ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.744m	34.547ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.149m	2.751ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.776m	2.172ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.734m	3.935ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.600m	4.540ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.858m	8.130ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.275h	31.801ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	26.664m	12.062ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.028m	2.296ms	1	1	100.00
V2		TOTAL			227	275	82.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.504m	3.670ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	40.480s	1.477ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.387h	71.388ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.129m	5.935ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.668m	10.617ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.916m	11.431ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.096m	10.706ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.166m		0	1	0.00
		rom_e2e_jtag_inject_dev	49.386s		0	1	0.00
		rom_e2e_jtag_inject_rma	56.900s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	16.805s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.676m	5.685ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.976m	3.003ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	6.261m	3.779ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	24.008m	10.673ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.467m	2.488ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.523m	5.067ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.019m	2.695ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.173m	5.734ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	5.210m	5.546ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.981m	4.299ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.393m	8.564ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.668m	10.617ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.916m	11.431ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.096m	10.706ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.551m	5.239ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.356m	5.951ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.373h	38.557ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.373h	38.557ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.548m	3.657ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.821m	4.518ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	49.037m	19.104ms	1	1	100.00
V3		TOTAL			19	23	82.61
	Unmapped tests	chip_sival_flash_info_access	2.588m	3.076ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.535m	5.368ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.141m	2.588ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.889m	3.552ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.488m	4.283ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	12.598s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.809m	3.115ms	1	1	100.00
		TOTAL			270	325	83.08

Failure Buckets

Job returned non-zero exit code has 42 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.86972147771508046175305572181996376135310320186558489931085028495263760180758
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 1.400s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.18575263927657411837223941181407805528483414974254196367362431504433056999935
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

      File "/nightly/runs/opentitan/rules/bitstreams.bzl", line 70, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:71:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 2.217s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_dev.83223751898483014038941202558081087374027486322351478700787764846495266923561
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:59:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (1 packages loaded, 26284 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 2.008s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod.81718405100331546469389725140646205722276910439638474015967883672079181267856
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log

      File "/nightly/runs/opentitan/rules/bitstreams.bzl", line 70, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:59:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 2.541s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.75938979137166645598779412672254529043737593051653010664331287344895281647451
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:71:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26284 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 1.809s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 37 more tests.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.40123864389541612162694648058481011308219078883715470453197986017081219251468
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3213.051232 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3213.051232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@99909) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.2467548250518261362659449074574921297816970406800842691174166464982539663694
Line 443, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4325.378730 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@99909) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4325.378730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.64342621004881704935916958486405008459279706926234217748658136908759675486679
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11927.472322 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11927.472322 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.78691943323291172755467820207831037902819574233093088503383246099977657038147
    Line 439, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34547.490640 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34547.490640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.92804273010196418714620546504822947791858851516174947250496982766155025340299
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2140.709280 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2140.709280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.36952403167322509967657743748096995073699130350824751117221354507292717195118
    Line 435, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2674.387464 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2674.387464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.33084711548247086432260600204432776834853951488979478205288019000594393244705
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2853.530797 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2853.530797 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44255) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.26408197422906670183115832283053806849088021546344144784056718952328334012929
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2093.910588 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44255) { a_addr: 'h1042c  a_data: 'hffea4e14  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3f  a_opcode: 'h4  a_user: 'h1957d  d_param: 'h0  d_source: 'h3f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2093.910588 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:708) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (x [0xx] vs * [*]) Major alert unexpectedly fired in cycle *. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.33135144040075908562493953075328582525801316646293934691666277196275605467250
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 1476.557094 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:708) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (x [0xx] vs 0 [0x0]) Major alert unexpectedly fired in cycle 0.
  UVM_INFO @ 1476.557094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.256385008436515851251477045360747857896712662314276476911138085430373948232
    Line 425, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2811.443000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2811.443000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.71109904564719483065685766504541885593495973869895572147122337425585034610099
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3486.473000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3486.473000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.22186614529406805469288081726761995377403165024406869198704463484188090661358
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 18641.972654 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 18641.972654 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31977) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.2027788775868211514402331399912164270307129784054390244472931697270487555303
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2408.255184 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31977) { a_addr: 'h10650  a_data: 'hd5f2f6ae  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he  a_opcode: 'h4  a_user: 'h1928c  d_param: 'h0  d_source: 'he  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2408.255184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---