ADC_CTRL Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	7.640s	5.920ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.940s	939.172us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.260s	403.536us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	39.410s	26.315ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.440s	673.188us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.370s	418.818us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.260s	403.536us	1	1	100.00
		adc_ctrl_csr_aliasing	2.440s	673.188us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	13.452m	499.090ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	9.121m	327.972ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	7.624m	331.312ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	8.853m	333.351ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	6.014m	524.408ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	4.076m	595.095ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.176m	530.999ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	2.485m	363.718ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.820s	5.511ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	5.870s	25.685ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.402m	75.073ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	9.350m	334.245ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.070s	495.909us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.010s	486.827us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.380s	371.548us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.380s	371.548us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.940s	939.172us	1	1	100.00
		adc_ctrl_csr_rw	2.260s	403.536us	1	1	100.00
		adc_ctrl_csr_aliasing	2.440s	673.188us	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.770s	5.343ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.940s	939.172us	1	1	100.00
		adc_ctrl_csr_rw	2.260s	403.536us	1	1	100.00
		adc_ctrl_csr_aliasing	2.440s	673.188us	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.770s	5.343ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	3.710s	4.194ms	1	1	100.00
		adc_ctrl_tl_intg_err	8.680s	4.202ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	8.680s	4.202ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	4.130s	2.251ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00