AES/MASKED Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	80.875us	1	1	100.00
V1	smoke	aes_smoke	5.000s	90.852us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	131.532us	1	1	100.00
V1	csr_rw	aes_csr_rw	4.000s	79.318us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	285.876us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	70.478us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	119.488us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	79.318us	1	1	100.00
		aes_csr_aliasing	5.000s	70.478us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	5.000s	90.852us	1	1	100.00
		aes_config_error	5.000s	74.350us	1	1	100.00
		aes_stress	5.000s	110.765us	1	1	100.00
V2	key_length	aes_smoke	5.000s	90.852us	1	1	100.00
		aes_config_error	5.000s	74.350us	1	1	100.00
		aes_stress	5.000s	110.765us	1	1	100.00
V2	back2back	aes_stress	5.000s	110.765us	1	1	100.00
		aes_b2b	10.000s	777.832us	1	1	100.00
V2	backpressure	aes_stress	5.000s	110.765us	1	1	100.00
V2	multi_message	aes_smoke	5.000s	90.852us	1	1	100.00
		aes_config_error	5.000s	74.350us	1	1	100.00
		aes_stress	5.000s	110.765us	1	1	100.00
		aes_alert_reset	6.000s	123.198us	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	83.459us	1	1	100.00
		aes_config_error	5.000s	74.350us	1	1	100.00
		aes_alert_reset	6.000s	123.198us	1	1	100.00
V2	trigger_clear_test	aes_clear	11.000s	436.467us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	404.818us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	123.198us	1	1	100.00
V2	stress	aes_stress	5.000s	110.765us	1	1	100.00
V2	sideload	aes_stress	5.000s	110.765us	1	1	100.00
		aes_sideload	6.000s	63.662us	1	1	100.00
V2	deinitialization	aes_deinit	6.000s	76.703us	1	1	100.00
V2	stress_all	aes_stress_all	58.000s	3.966ms	1	1	100.00
V2	alert_test	aes_alert_test	5.000s	51.648us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	183.390us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	183.390us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	131.532us	1	1	100.00
		aes_csr_rw	4.000s	79.318us	1	1	100.00
		aes_csr_aliasing	5.000s	70.478us	1	1	100.00
		aes_same_csr_outstanding	5.000s	129.895us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	131.532us	1	1	100.00
		aes_csr_rw	4.000s	79.318us	1	1	100.00
		aes_csr_aliasing	5.000s	70.478us	1	1	100.00
		aes_same_csr_outstanding	5.000s	129.895us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	5.000s	64.500us	1	1	100.00
V2S	fault_inject	aes_fi	5.000s	167.400us	1	1	100.00
		aes_control_fi	39.000s	10.006ms	0	1	0.00
		aes_cipher_fi	5.000s	46.734us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	137.448us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	137.448us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	137.448us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	137.448us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	383.839us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	315.429us	1	1	100.00
		aes_tl_intg_err	5.000s	586.752us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	586.752us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	123.198us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	137.448us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	90.852us	1	1	100.00
		aes_stress	5.000s	110.765us	1	1	100.00
		aes_alert_reset	6.000s	123.198us	1	1	100.00
		aes_core_fi	5.000s	149.164us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	137.448us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	61.650us	1	1	100.00
		aes_stress	5.000s	110.765us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	110.765us	1	1	100.00
		aes_sideload	6.000s	63.662us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	61.650us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	61.650us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	61.650us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	61.650us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	61.650us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	110.765us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	110.765us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	167.400us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	167.400us	1	1	100.00
		aes_control_fi	39.000s	10.006ms	0	1	0.00
		aes_cipher_fi	5.000s	46.734us	1	1	100.00
		aes_ctr_fi	5.000s	118.435us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	167.400us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	167.400us	1	1	100.00
		aes_control_fi	39.000s	10.006ms	0	1	0.00
		aes_cipher_fi	5.000s	46.734us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	5.000s	46.734us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	167.400us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	167.400us	1	1	100.00
		aes_control_fi	39.000s	10.006ms	0	1	0.00
		aes_ctr_fi	5.000s	118.435us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	167.400us	1	1	100.00
		aes_control_fi	39.000s	10.006ms	0	1	0.00
		aes_cipher_fi	5.000s	46.734us	1	1	100.00
		aes_ctr_fi	5.000s	118.435us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	123.198us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	167.400us	1	1	100.00
		aes_control_fi	39.000s	10.006ms	0	1	0.00
		aes_cipher_fi	5.000s	46.734us	1	1	100.00
		aes_ctr_fi	5.000s	118.435us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	167.400us	1	1	100.00
		aes_control_fi	39.000s	10.006ms	0	1	0.00
		aes_cipher_fi	5.000s	46.734us	1	1	100.00
		aes_ctr_fi	5.000s	118.435us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	167.400us	1	1	100.00
		aes_control_fi	39.000s	10.006ms	0	1	0.00
		aes_ctr_fi	5.000s	118.435us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	167.400us	1	1	100.00
		aes_control_fi	39.000s	10.006ms	0	1	0.00
		aes_cipher_fi	5.000s	46.734us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	21.000s	367.782us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 1 failures:

  • Test aes_control_fi has 1 failures.

    • 0.aes_control_fi.38292541111352091429884621323709241893726557395017426924770164129584114076766
      Line 137, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log

        UVM_FATAL @ 10005832920 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10005832920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.99949936716962594979225204792956914968888548956746537686246460173423332941084
      Line 686, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 367781821 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.keymgr_sideload_agent.sequencer.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 367781821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---