EDN Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.840s	17.742us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.660s	32.894us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.810s	23.686us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.500s	146.548us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.880s	82.060us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.120s	178.898us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.810s	23.686us	1	1	100.00
		edn_csr_aliasing	1.880s	82.060us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.010s	66.598us	1	1	100.00
V2	csrng_commands	edn_genbits	2.010s	66.598us	1	1	100.00
V2	genbits	edn_genbits	2.010s	66.598us	1	1	100.00
V2	interrupts	edn_intr	1.990s	22.357us	1	1	100.00
V2	alerts	edn_alert	1.970s	26.057us	1	1	100.00
V2	errs	edn_err	1.720s	32.118us	1	1	100.00
V2	disable	edn_disable	1.650s	13.822us	1	1	100.00
		edn_disable_auto_req_mode	1.950s	127.951us	1	1	100.00
V2	stress_all	edn_stress_all	2.400s	281.948us	1	1	100.00
V2	intr_test	edn_intr_test	1.700s	22.464us	1	1	100.00
V2	alert_test	edn_alert_test	1.580s	25.665us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.890s	143.220us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.890s	143.220us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.660s	32.894us	1	1	100.00
		edn_csr_rw	1.810s	23.686us	1	1	100.00
		edn_csr_aliasing	1.880s	82.060us	1	1	100.00
		edn_same_csr_outstanding	2.020s	33.472us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.660s	32.894us	1	1	100.00
		edn_csr_rw	1.810s	23.686us	1	1	100.00
		edn_csr_aliasing	1.880s	82.060us	1	1	100.00
		edn_same_csr_outstanding	2.020s	33.472us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	9.820s	7.954ms	1	1	100.00
		edn_tl_intg_err	3.050s	1.032ms	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.760s	47.258us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.970s	26.057us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	9.820s	7.954ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	9.820s	7.954ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	9.820s	7.954ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	9.820s	7.954ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.970s	26.057us	1	1	100.00
		edn_sec_cm	9.820s	7.954ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.970s	26.057us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.050s	1.032ms	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	47.170s	9.873ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00