HMAC Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.160s 500.118us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.830s 93.447us 1 1 100.00
V1 csr_rw hmac_csr_rw 2.060s 75.177us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.890s 397.004us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.160s 304.341us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.320s 168.018us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 2.060s 75.177us 1 1 100.00
hmac_csr_aliasing 3.160s 304.341us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 17.470s 2.662ms 1 1 100.00
V2 back_pressure hmac_back_pressure 39.970s 3.195ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.940s 164.761us 1 1 100.00
hmac_test_sha384_vectors 5.742m 11.221ms 1 1 100.00
hmac_test_sha512_vectors 20.500s 1.182ms 1 1 100.00
hmac_test_hmac256_vectors 11.630s 1.483ms 1 1 100.00
hmac_test_hmac384_vectors 13.150s 280.940us 1 1 100.00
hmac_test_hmac512_vectors 9.120s 236.796us 1 1 100.00
V2 burst_wr hmac_burst_wr 14.590s 1.101ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 13.667m 5.676ms 1 1 100.00
V2 error hmac_error 10.090s 494.070us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.032m 6.822ms 1 1 100.00
V2 save_and_restore hmac_smoke 7.160s 500.118us 1 1 100.00
hmac_long_msg 17.470s 2.662ms 1 1 100.00
hmac_back_pressure 39.970s 3.195ms 1 1 100.00
hmac_datapath_stress 13.667m 5.676ms 1 1 100.00
hmac_burst_wr 14.590s 1.101ms 1 1 100.00
hmac_stress_all 8.727m 49.423ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.160s 500.118us 1 1 100.00
hmac_long_msg 17.470s 2.662ms 1 1 100.00
hmac_back_pressure 39.970s 3.195ms 1 1 100.00
hmac_datapath_stress 13.667m 5.676ms 1 1 100.00
hmac_wipe_secret 1.032m 6.822ms 1 1 100.00
hmac_test_sha256_vectors 8.940s 164.761us 1 1 100.00
hmac_test_sha384_vectors 5.742m 11.221ms 1 1 100.00
hmac_test_sha512_vectors 20.500s 1.182ms 1 1 100.00
hmac_test_hmac256_vectors 11.630s 1.483ms 1 1 100.00
hmac_test_hmac384_vectors 13.150s 280.940us 1 1 100.00
hmac_test_hmac512_vectors 9.120s 236.796us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.160s 500.118us 1 1 100.00
hmac_long_msg 17.470s 2.662ms 1 1 100.00
hmac_back_pressure 39.970s 3.195ms 1 1 100.00
hmac_datapath_stress 13.667m 5.676ms 1 1 100.00
hmac_burst_wr 14.590s 1.101ms 1 1 100.00
hmac_error 10.090s 494.070us 1 1 100.00
hmac_wipe_secret 1.032m 6.822ms 1 1 100.00
hmac_test_sha256_vectors 8.940s 164.761us 1 1 100.00
hmac_test_sha384_vectors 5.742m 11.221ms 1 1 100.00
hmac_test_sha512_vectors 20.500s 1.182ms 1 1 100.00
hmac_test_hmac256_vectors 11.630s 1.483ms 1 1 100.00
hmac_test_hmac384_vectors 13.150s 280.940us 1 1 100.00
hmac_test_hmac512_vectors 9.120s 236.796us 1 1 100.00
hmac_stress_all 8.727m 49.423ms 1 1 100.00
V2 stress_all hmac_stress_all 8.727m 49.423ms 1 1 100.00
V2 alert_test hmac_alert_test 1.440s 13.803us 1 1 100.00
V2 intr_test hmac_intr_test 1.550s 14.977us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.590s 83.769us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.590s 83.769us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.830s 93.447us 1 1 100.00
hmac_csr_rw 2.060s 75.177us 1 1 100.00
hmac_csr_aliasing 3.160s 304.341us 1 1 100.00
hmac_same_csr_outstanding 2.670s 186.675us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.830s 93.447us 1 1 100.00
hmac_csr_rw 2.060s 75.177us 1 1 100.00
hmac_csr_aliasing 3.160s 304.341us 1 1 100.00
hmac_same_csr_outstanding 2.670s 186.675us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.200s 591.768us 1 1 100.00
hmac_tl_intg_err 2.800s 84.905us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.800s 84.905us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.160s 500.118us 1 1 100.00
V3 stress_reset hmac_stress_reset 4.930s 314.072us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.160m 17.697ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.960s 110.005us 1 1 100.00
TOTAL 28 28 100.00