I2C Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	17.580s	6.497ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.040s	1.021ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.700s	20.638us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.770s	21.297us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.000s	118.033us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.550s	428.354us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.790s	52.957us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.770s	21.297us	1	1	100.00
		i2c_csr_aliasing	2.550s	428.354us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	6.790s	220.570us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	6.148m	90.335ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	16.550s	7.369ms	1	1	100.00
V2	host_override	i2c_host_override	1.650s	27.630us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.090m	14.442ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	25.940s	3.128ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.950s	133.633us	1	1	100.00
		i2c_host_fifo_fmt_empty	10.190s	652.172us	1	1	100.00
		i2c_host_fifo_reset_rx	4.070s	119.757us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.321m	8.465ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.790s	5.059ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.200s	260.080us	0	1	0.00
V2	target_glitch	i2c_target_glitch	8.950s	9.520ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	39.850s	71.593ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.710s	1.923ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	39.310s	1.226ms	1	1	100.00
		i2c_target_intr_smoke	4.810s	4.012ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.740s	269.607us	1	1	100.00
		i2c_target_fifo_reset_tx	2.420s	742.332us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	3.670s	8.525ms	1	1	100.00
		i2c_target_stress_rd	39.310s	1.226ms	1	1	100.00
		i2c_target_intr_stress_wr	29.670s	10.339ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.920s	1.373ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.260s	165.492us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.320s	2.913ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.790s	3.966ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.440s	646.112us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.020s	155.441us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	16.550s	7.369ms	1	1	100.00
		i2c_host_perf_precise	22.690s	3.106ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.790s	5.059ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.410s	93.093us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.870s	675.323us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.530s	1.101ms	1	1	100.00
		i2c_target_nack_txstretch	2.030s	173.638us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	6.920s	879.614us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.720s	1.944ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.690s	17.607us	1	1	100.00
V2	intr_test	i2c_intr_test	1.630s	23.391us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.970s	140.800us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.970s	140.800us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.700s	20.638us	1	1	100.00
		i2c_csr_rw	1.770s	21.297us	1	1	100.00
		i2c_csr_aliasing	2.550s	428.354us	1	1	100.00
		i2c_same_csr_outstanding	1.690s	35.571us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.700s	20.638us	1	1	100.00
		i2c_csr_rw	1.770s	21.297us	1	1	100.00
		i2c_csr_aliasing	2.550s	428.354us	1	1	100.00
		i2c_same_csr_outstanding	1.690s	35.571us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.660s	153.654us	1	1	100.00
		i2c_sec_cm	1.820s	93.919us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.660s	153.654us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	30.510s	3.583ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.000s	202.034us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	12.540s	1.052ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.102911843863567740665695329157110206107294075680780697426493159719356092316553
      Line 98, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3582894958 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3582894958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.6825550716297513269920817624906629775667684055939651401491743692203016780140
      Line 96, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1051931372 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1051931372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.22760401016800758868307043293361431569672423594009160110672356751197388869239
      Line 167, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 90334821196 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @10114484
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.100848977773171435124809881954791425458629566448863211450395849824986058479204
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 202034342 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 202034342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.22473875705407175559137783190999585592834538458237393649717957521541784815945
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 260079758 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.71492234909685193331171120396144954257485473350063120991012500755366497626392
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 173637808 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 173637808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---