KEYMGR Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.770s	654.060us	1	1	100.00
V1	random	keymgr_random	5.020s	432.578us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.270s	74.029us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.800s	19.340us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.210s	623.219us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	5.680s	726.686us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.950s	338.534us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.800s	19.340us	1	1	100.00
		keymgr_csr_aliasing	5.680s	726.686us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	30.250s	5.493ms	1	1	100.00
V2	sideload	keymgr_sideload	5.220s	407.274us	1	1	100.00
		keymgr_sideload_kmac	3.440s	92.681us	1	1	100.00
		keymgr_sideload_aes	2.760s	139.108us	1	1	100.00
		keymgr_sideload_otbn	2.250s	23.424us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.290s	46.236us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.590s	57.613us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.870s	64.259us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	2.920s	149.845us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	8.790s	3.607ms	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.380s	57.327us	1	1	100.00
V2	stress_all	keymgr_stress_all	9.400s	472.724us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.720s	15.095us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.620s	13.807us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.930s	219.491us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.930s	219.491us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.270s	74.029us	1	1	100.00
		keymgr_csr_rw	1.800s	19.340us	1	1	100.00
		keymgr_csr_aliasing	5.680s	726.686us	1	1	100.00
		keymgr_same_csr_outstanding	1.700s	20.143us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.270s	74.029us	1	1	100.00
		keymgr_csr_rw	1.800s	19.340us	1	1	100.00
		keymgr_csr_aliasing	5.680s	726.686us	1	1	100.00
		keymgr_same_csr_outstanding	1.700s	20.143us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	9.460s	3.283ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	9.460s	3.283ms	1	1	100.00
		keymgr_tl_intg_err	4.190s	419.712us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.060s	76.196us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.060s	76.196us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.060s	76.196us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.060s	76.196us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	2.320s	67.094us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	9.460s	3.283ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	9.460s	3.283ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.190s	419.712us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.060s	76.196us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	30.250s	5.493ms	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	5.020s	432.578us	1	1	100.00
		keymgr_csr_rw	1.800s	19.340us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	5.020s	432.578us	1	1	100.00
		keymgr_csr_rw	1.800s	19.340us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	5.020s	432.578us	1	1	100.00
		keymgr_csr_rw	1.800s	19.340us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.590s	57.613us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	8.790s	3.607ms	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	8.790s	3.607ms	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	5.020s	432.578us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	8.000s	1.602ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	9.460s	3.283ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	9.460s	3.283ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	9.460s	3.283ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	5.270s	1.015ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.590s	57.613us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	9.460s	3.283ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	9.460s	3.283ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	9.460s	3.283ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	5.270s	1.015ms	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	5.270s	1.015ms	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	9.460s	3.283ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	5.270s	1.015ms	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	9.460s	3.283ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	5.270s	1.015ms	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	10.070s	2.534ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	30	93.33

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.63445659785942049611379056327781682558047307594620411541268237462752263821325
      Line 78, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
        UVM_ERROR @  67093984 ps: (keymgr_csr_assert_fpv.sv:469) [ASSERT FAILED] attest_sw_binding_7_rd_A
        UVM_INFO @  67093984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.58310538614011860422778306105120597357704145198502435022897793681381639587965
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
        UVM_ERROR @  20142560 ps: (keymgr_csr_assert_fpv.sv:454) [ASSERT FAILED] attest_sw_binding_4_rd_A
        UVM_INFO @  20142560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---