KMAC/MASKED Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	55.970s	3.785ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.820s	36.976us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.630s	139.844us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	5.890s	295.225us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.260s	7.672ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.490s	70.093us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.630s	139.844us	1	1	100.00
		kmac_csr_aliasing	8.260s	7.672ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.610s	67.823us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.870s	95.663us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.548m	250.612ms	1	1	100.00
V2	burst_write	kmac_burst_write	46.130s	5.838ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.610s	8.182ms	1	1	100.00
		kmac_test_vectors_sha3_256	21.298m	33.452ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.125m	55.624ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.050s	1.385ms	1	1	100.00
		kmac_test_vectors_shake_128	34.951m	72.759ms	1	1	100.00
		kmac_test_vectors_shake_256	27.407m	215.645ms	1	1	100.00
		kmac_test_vectors_kmac	3.320s	403.002us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.710s	32.962us	1	1	100.00
V2	sideload	kmac_sideload	59.970s	2.677ms	1	1	100.00
V2	app	kmac_app	3.156m	14.209ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.980m	33.669ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.288m	15.106ms	1	1	100.00
V2	error	kmac_error	3.029m	3.548ms	1	1	100.00
V2	key_error	kmac_key_error	1.940s	38.315us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	5.170s	176.460us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	4.780s	76.753us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.750s	58.109us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	31.650s	11.166ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	8.060s	536.813us	1	1	100.00
V2	stress_all	kmac_stress_all	52.530s	14.696ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.770s	49.313us	1	1	100.00
V2	alert_test	kmac_alert_test	1.600s	23.511us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.720s	893.725us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.720s	893.725us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.820s	36.976us	1	1	100.00
		kmac_csr_rw	1.630s	139.844us	1	1	100.00
		kmac_csr_aliasing	8.260s	7.672ms	1	1	100.00
		kmac_same_csr_outstanding	2.680s	105.934us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.820s	36.976us	1	1	100.00
		kmac_csr_rw	1.630s	139.844us	1	1	100.00
		kmac_csr_aliasing	8.260s	7.672ms	1	1	100.00
		kmac_same_csr_outstanding	2.680s	105.934us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.250s	35.759us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.250s	35.759us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.250s	35.759us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.250s	35.759us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.870s	620.777us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	30.120s	10.325ms	1	1	100.00
		kmac_tl_intg_err	4.100s	223.872us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.100s	223.872us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	8.060s	536.813us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	55.970s	3.785ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	59.970s	2.677ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.250s	35.759us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	30.120s	10.325ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	30.120s	10.325ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	30.120s	10.325ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	55.970s	3.785ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	8.060s	536.813us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	30.120s	10.325ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	32.290s	10.809ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	55.970s	3.785ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	54.730s	2.924ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.50042196783665452745230285945811284857658668921699579504946406206588605078943
      Line 202, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2924014751 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2924014751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---