ROM_CTRL/32KB Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.430s 889.774us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.040s 567.027us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.070s 208.854us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.280s 239.343us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.930s 385.769us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.020s 135.943us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.070s 208.854us 1 1 100.00
rom_ctrl_csr_aliasing 3.930s 385.769us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.960s 211.039us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.070s 2.007ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.760s 246.894us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 10.310s 1.742ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.940s 716.143us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.250s 127.258us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.110s 318.316us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.110s 318.316us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.040s 567.027us 1 1 100.00
rom_ctrl_csr_rw 4.070s 208.854us 1 1 100.00
rom_ctrl_csr_aliasing 3.930s 385.769us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.450s 575.332us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.040s 567.027us 1 1 100.00
rom_ctrl_csr_rw 4.070s 208.854us 1 1 100.00
rom_ctrl_csr_aliasing 3.930s 385.769us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.450s 575.332us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.133m 4.361ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 22.820s 848.573us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.481m 359.207us 1 1 100.00
rom_ctrl_tl_intg_err 21.450s 790.277us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.481m 359.207us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.481m 359.207us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.133m 4.361ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.133m 4.361ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.133m 4.361ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.133m 4.361ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.133m 4.361ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.481m 359.207us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.481m 359.207us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.430s 889.774us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.430s 889.774us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.430s 889.774us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 21.450s 790.277us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.133m 4.361ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.940s 716.143us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.133m 4.361ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.133m 4.361ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.133m 4.361ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 22.820s 848.573us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.481m 359.207us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 53.900s 5.435ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00