ROM_CTRL/64KB Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.020s 592.911us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.970s 300.984us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.650s 1.067ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.410s 1.066ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.920s 555.672us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.460s 325.780us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.650s 1.067ms 1 1 100.00
rom_ctrl_csr_aliasing 6.920s 555.672us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.920s 305.728us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 8.710s 3.963ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.620s 733.916us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 28.070s 4.227ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.150s 1.079ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.290s 295.700us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.340s 299.072us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.340s 299.072us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.970s 300.984us 1 1 100.00
rom_ctrl_csr_rw 6.650s 1.067ms 1 1 100.00
rom_ctrl_csr_aliasing 6.920s 555.672us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.410s 212.477us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.970s 300.984us 1 1 100.00
rom_ctrl_csr_rw 6.650s 1.067ms 1 1 100.00
rom_ctrl_csr_aliasing 6.920s 555.672us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.410s 212.477us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.384m 2.415ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 30.060s 1.087ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.564m 3.045ms 1 1 100.00
rom_ctrl_tl_intg_err 34.060s 946.193us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.564m 3.045ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.564m 3.045ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.384m 2.415ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.384m 2.415ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.384m 2.415ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.384m 2.415ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.384m 2.415ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.564m 3.045ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.564m 3.045ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.020s 592.911us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.020s 592.911us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.020s 592.911us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 34.060s 946.193us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.384m 2.415ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.150s 1.079ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.384m 2.415ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.384m 2.415ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.384m 2.415ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 30.060s 1.087ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.564m 3.045ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 50.300s 7.587ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00