RV_TIMER Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.470s	14.764us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.640s	19.107us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.570s	34.695us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.190s	70.359us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.520s	58.415us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.750s	38.654us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.570s	34.695us	1	1	100.00
		rv_timer_csr_aliasing	1.520s	58.415us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	11.620s	9.837ms	1	1	100.00
V2	disabled	rv_timer_disabled	2.280s	1.925ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	4.695m	271.518ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	4.695m	271.518ms	1	1	100.00
V2	stress	rv_timer_stress_all	7.310s	6.093ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.530s	27.046us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.710s	25.689us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.100s	253.457us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.100s	253.457us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.640s	19.107us	1	1	100.00
		rv_timer_csr_rw	1.570s	34.695us	1	1	100.00
		rv_timer_csr_aliasing	1.520s	58.415us	1	1	100.00
		rv_timer_same_csr_outstanding	1.610s	15.207us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.640s	19.107us	1	1	100.00
		rv_timer_csr_rw	1.570s	34.695us	1	1	100.00
		rv_timer_csr_aliasing	1.520s	58.415us	1	1	100.00
		rv_timer_same_csr_outstanding	1.610s	15.207us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.740s	405.998us	1	1	100.00
		rv_timer_tl_intg_err	2.040s	170.253us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.040s	170.253us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	21.740s	16.727ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.500s	11.775us	1	1	100.00
		rv_timer_max	1.400s	36.450us	1	1	100.00
		TOTAL			19	19	100.00