SPI_DEVICE/1R1W Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.137m	9.155ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.130s	89.581us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.790s	216.378us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.910s	6.285ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.070s	2.336ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.750s	160.874us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.790s	216.378us	1	1	100.00
		spi_device_csr_aliasing	17.070s	2.336ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.630s	17.269us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.250s	84.117us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.790s	69.837us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.610s	5.113us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.520s	5.561us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.590s	964.896us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.590s	964.896us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.900s	1.721ms	1	1	100.00
		spi_device_tpm_sts_read	1.640s	80.342us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	7.590s	2.328ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	11.580s	30.552ms	1	1	100.00
		spi_device_flash_all	13.750s	3.028ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.590s	1.542ms	1	1	100.00
		spi_device_flash_all	13.750s	3.028ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.590s	1.542ms	1	1	100.00
		spi_device_flash_all	13.750s	3.028ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	13.750s	3.028ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.780s	106.800us	1	1	100.00
		spi_device_flash_all	13.750s	3.028ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.780s	106.800us	1	1	100.00
		spi_device_flash_all	13.750s	3.028ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.780s	106.800us	1	1	100.00
		spi_device_flash_all	13.750s	3.028ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.780s	106.800us	1	1	100.00
		spi_device_flash_all	13.750s	3.028ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.780s	106.800us	1	1	100.00
		spi_device_flash_all	13.750s	3.028ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.030s	1.850ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.950s	1.439ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.950s	1.439ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.950s	1.439ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	31.080s	3.173ms	1	1	100.00
		spi_device_read_buffer_direct	6.630s	1.898ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.950s	1.439ms	1	1	100.00
		spi_device_flash_all	13.750s	3.028ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	13.750s	3.028ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	13.750s	3.028ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.680s	92.434us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.680s	92.434us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.137m	9.155ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.156m	8.706ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.660s	164.540us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.520s	12.090us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.580s	11.625us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.070s	240.887us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.070s	240.887us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.130s	89.581us	1	1	100.00
		spi_device_csr_rw	2.790s	216.378us	1	1	100.00
		spi_device_csr_aliasing	17.070s	2.336ms	1	1	100.00
		spi_device_same_csr_outstanding	3.230s	104.695us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.130s	89.581us	1	1	100.00
		spi_device_csr_rw	2.790s	216.378us	1	1	100.00
		spi_device_csr_aliasing	17.070s	2.336ms	1	1	100.00
		spi_device_same_csr_outstanding	3.230s	104.695us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.810s	86.562us	1	1	100.00
		spi_device_tl_intg_err	5.810s	457.980us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.810s	457.980us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.447m	19.786ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.66802629699648007842658628574988159093967953459859187222701380382275190027776
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3353014 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[100])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3353014 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3353014 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[996])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.17108187053074013975740462527223360119437793409074477708506180353836734166573
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3039954 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x443a75 [10001000011101001110101] vs 0x0 [0])
        UVM_ERROR @   3073954 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb43223 [101101000011001000100011] vs 0x0 [0])
        UVM_ERROR @   3133954 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x375348 [1101110101001101001000] vs 0x0 [0])
        UVM_ERROR @   3158954 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x93c627 [100100111100011000100111] vs 0x0 [0])
        UVM_ERROR @   3176954 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf3fe7a [111100111111111001111010] vs 0x0 [0])