SPI_DEVICE/2P Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.610s	12.417ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.900s	344.542us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.410s	324.015us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.920s	3.680ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.010s	618.296us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.720s	40.588us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.410s	324.015us	1	1	100.00
		spi_device_csr_aliasing	11.010s	618.296us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.460s	114.697us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.440s	100.930us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.590s	48.821us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.700s	33.127us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.650s	28.302us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.960s	100.384us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.960s	100.384us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	13.330s	25.490ms	1	1	100.00
		spi_device_tpm_sts_read	1.590s	89.999us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.590s	3.527ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.990s	204.235us	1	1	100.00
		spi_device_flash_all	40.940s	21.628ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.510s	146.010us	1	1	100.00
		spi_device_flash_all	40.940s	21.628ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.510s	146.010us	1	1	100.00
		spi_device_flash_all	40.940s	21.628ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	40.940s	21.628ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	9.500s	1.485ms	1	1	100.00
		spi_device_flash_all	40.940s	21.628ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	9.500s	1.485ms	1	1	100.00
		spi_device_flash_all	40.940s	21.628ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	9.500s	1.485ms	1	1	100.00
		spi_device_flash_all	40.940s	21.628ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	9.500s	1.485ms	1	1	100.00
		spi_device_flash_all	40.940s	21.628ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	9.500s	1.485ms	1	1	100.00
		spi_device_flash_all	40.940s	21.628ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.780s	113.333us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	8.950s	6.986ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	8.950s	6.986ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	8.950s	6.986ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.280s	1.038ms	1	1	100.00
		spi_device_read_buffer_direct	4.940s	1.931ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	8.950s	6.986ms	1	1	100.00
		spi_device_flash_all	40.940s	21.628ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	40.940s	21.628ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	40.940s	21.628ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	7.220s	2.153ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	7.220s	2.153ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.610s	12.417ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.859m	32.353ms	1	1	100.00
V2	stress_all	spi_device_stress_all	36.490s	18.928ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.550s	127.216us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.520s	15.052us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.200s	25.000us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.200s	25.000us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.900s	344.542us	1	1	100.00
		spi_device_csr_rw	2.410s	324.015us	1	1	100.00
		spi_device_csr_aliasing	11.010s	618.296us	1	1	100.00
		spi_device_same_csr_outstanding	2.990s	45.227us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.900s	344.542us	1	1	100.00
		spi_device_csr_rw	2.410s	324.015us	1	1	100.00
		spi_device_csr_aliasing	11.010s	618.296us	1	1	100.00
		spi_device_same_csr_outstanding	2.990s	45.227us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.960s	520.987us	1	1	100.00
		spi_device_tl_intg_err	9.570s	2.386ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.570s	2.386ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.260m	203.961ms	1	1	100.00
		TOTAL			33	33	100.00