SRAM_CTRL/MAIN Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	49.850s	958.347us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.730s	41.972us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.640s	15.347us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.480s	81.678us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.600s	47.580us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.460s	356.260us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.640s	15.347us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	47.580us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.743m	15.183ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.634m	1.602ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.208m	4.419ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.034m	4.273ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	29.455m	405.174ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.522m	17.655ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	27.500s	6.435ms	1	1	100.00
V2	executable	sram_ctrl_executable	10.152m	37.574ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	32.720s	4.919ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.518m	12.255ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	15.380s	2.840ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	29.620s	762.777us	1	1	100.00
		sram_ctrl_throughput_w_readback	12.220s	754.246us	1	1	100.00
V2	regwen	sram_ctrl_regwen	15.006m	45.098ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.930s	348.562us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	43.435m	69.728ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.580s	45.198us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.500s	460.989us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.500s	460.989us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.730s	41.972us	1	1	100.00
		sram_ctrl_csr_rw	1.640s	15.347us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	47.580us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.800s	52.750us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.730s	41.972us	1	1	100.00
		sram_ctrl_csr_rw	1.640s	15.347us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	47.580us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.800s	52.750us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	37.200s	29.402ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.560s	2.857us	0	1	0.00
		sram_ctrl_tl_intg_err	2.190s	108.746us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.560s	2.857us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.190s	108.746us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	15.006m	45.098ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	15.006m	45.098ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.640s	15.347us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.152m	37.574ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.152m	37.574ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.152m	37.574ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	27.500s	6.435ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	9.020s	3.914ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	37.200s	29.402ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	7.390s	1.318ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	49.850s	958.347us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	49.850s	958.347us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.152m	37.574ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.560s	2.857us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	27.500s	6.435ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.560s	2.857us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.560s	2.857us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	49.850s	958.347us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.560s	2.857us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	18.250s	3.463ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.53918582223602312149562757106515851093409741497474415233331221524718665320451
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1317610955 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x69) != exp (0xc)
        UVM_INFO @ 1317610955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.104799432212193477482612061671046021431964977471762525926580907855742753171405
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2856733 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2856733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---