SRAM_CTRL/RET Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 6.810s 607.805us 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.650s 21.393us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 1.500s 11.574us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.790s 103.693us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.580s 20.186us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.300s 115.313us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.500s 11.574us 1 1 100.00
sram_ctrl_csr_aliasing 1.580s 20.186us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 7.090s 216.406us 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 4.810s 557.147us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 6.188m 12.322ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 2.986m 2.668ms 1 1 100.00
V2 bijection sram_ctrl_bijection 40.300s 6.846ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 4.883m 12.037ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 5.840s 2.864ms 1 1 100.00
V2 executable sram_ctrl_executable 3.427m 8.368ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 1.830s 74.508us 1 1 100.00
sram_ctrl_partial_access_b2b 2.406m 5.782ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 16.620s 675.027us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.880s 129.603us 1 1 100.00
sram_ctrl_throughput_w_readback 1.860s 142.983us 1 1 100.00
V2 regwen sram_ctrl_regwen 3.065m 5.395ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 1.850s 49.037us 1 1 100.00
V2 stress_all sram_ctrl_stress_all 21.956m 341.263ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 1.530s 16.102us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 2.990s 535.768us 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 2.990s 535.768us 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.650s 21.393us 1 1 100.00
sram_ctrl_csr_rw 1.500s 11.574us 1 1 100.00
sram_ctrl_csr_aliasing 1.580s 20.186us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.620s 15.515us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.650s 21.393us 1 1 100.00
sram_ctrl_csr_rw 1.500s 11.574us 1 1 100.00
sram_ctrl_csr_aliasing 1.580s 20.186us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.620s 15.515us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 2.940s 280.335us 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 1.630s 4.406us 0 1 0.00
sram_ctrl_tl_intg_err 2.290s 190.555us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 1.630s 4.406us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.290s 190.555us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 3.065m 5.395ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 3.065m 5.395ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.500s 11.574us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 3.427m 8.368ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 3.427m 8.368ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 3.427m 8.368ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 5.840s 2.864ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 1.780s 39.119us 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 2.940s 280.335us 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 1.760s 31.542us 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 6.810s 607.805us 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 6.810s 607.805us 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 3.427m 8.368ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 1.630s 4.406us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 5.840s 2.864ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 1.630s 4.406us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 1.630s 4.406us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 6.810s 607.805us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 1.630s 4.406us 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 54.060s 1.975ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets