SYSRST_CTRL Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	5.040s	2.117ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	4.480s	2.473ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	5.940s	2.426ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	4.030s	2.280ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	13.900s	6.050ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	5.210s	2.039ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	2.220m	74.050ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	8.670s	2.585ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.620s	2.078ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	5.210s	2.039ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	8.670s	2.585ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	2.682m	76.233ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	1.238m	71.210ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	4.730s	2.904ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	2.960s	2.696ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	4.110s	2.512ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	2.260s	2.045ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	2.490s	3.208ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.610s	2.643ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	6.450s	4.244ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	20.310s	34.351ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	1.018m	328.120ms	0	1	0.00
V2	alert_test	sysrst_ctrl_alert_test	3.710s	2.019ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	2.680s	2.037ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	6.310s	2.069ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	6.310s	2.069ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	13.900s	6.050ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.210s	2.039ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	8.670s	2.585ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	28.850s	9.911ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	13.900s	6.050ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.210s	2.039ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	8.670s	2.585ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	28.850s	9.911ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	23.390s	22.037ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	22.950s	22.314ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	22.950s	22.314ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	9.370s	8.687ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) has 1 failures:

  • Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.sysrst_ctrl_stress_all_with_rand_reset.76948318880866933095020871042507677964128820267536949266492334162767478066112
      Line 430, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8686776141 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (0 [0x0] vs 1 [0x1])
        UVM_ERROR @ 8686776141 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 8686776141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:

  • Test sysrst_ctrl_stress_all has 1 failures.

    • 0.sysrst_ctrl_stress_all.98250063661749437953535761142842534644942637145273644551250779475037047111450
      Line 423, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 328119855408 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 328119980408 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 328119980408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---