UART Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.260s	107.345us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.620s	21.599us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.750s	76.623us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.340s	71.091us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.720s	161.891us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.880s	59.215us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.750s	76.623us	1	1	100.00
		uart_csr_aliasing	1.720s	161.891us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	53.800s	175.146ms	1	1	100.00
V2	parity	uart_smoke	2.260s	107.345us	1	1	100.00
		uart_tx_rx	53.800s	175.146ms	1	1	100.00
V2	parity_error	uart_intr	11.650s	28.689ms	1	1	100.00
		uart_rx_parity_err	2.017m	207.775ms	1	1	100.00
V2	watermark	uart_tx_rx	53.800s	175.146ms	1	1	100.00
		uart_intr	11.650s	28.689ms	1	1	100.00
V2	fifo_full	uart_fifo_full	52.980s	80.067ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	27.340s	23.714ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	32.860s	27.936ms	1	1	100.00
V2	rx_frame_err	uart_intr	11.650s	28.689ms	1	1	100.00
V2	rx_break_err	uart_intr	11.650s	28.689ms	1	1	100.00
V2	rx_timeout	uart_intr	11.650s	28.689ms	1	1	100.00
V2	perf	uart_perf	1.862m	11.483ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.280s	4.856ms	1	1	100.00
V2	line_loopback	uart_loopback	5.280s	4.856ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.122m	147.659ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.820s	4.121ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.330s	917.349us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	2.600s	1.741ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	11.978m	129.281ms	1	1	100.00
V2	stress_all	uart_stress_all	1.327m	62.868ms	1	1	100.00
V2	alert_test	uart_alert_test	1.450s	45.635us	1	1	100.00
V2	intr_test	uart_intr_test	1.490s	30.397us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.770s	90.449us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.770s	90.449us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.620s	21.599us	1	1	100.00
		uart_csr_rw	1.750s	76.623us	1	1	100.00
		uart_csr_aliasing	1.720s	161.891us	1	1	100.00
		uart_same_csr_outstanding	1.660s	53.789us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.620s	21.599us	1	1	100.00
		uart_csr_rw	1.750s	76.623us	1	1	100.00
		uart_csr_aliasing	1.720s	161.891us	1	1	100.00
		uart_same_csr_outstanding	1.660s	53.789us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.740s	80.192us	1	1	100.00
		uart_tl_intg_err	2.770s	95.265us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.770s	95.265us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	25.390s	6.731ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00