CHIP Simulation Results

Tuesday May 20 2025 20:24:38 UTC

GitHub Revision: `0463149`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.364m	2.561ms	1	1	100.00
		chip_sw_example_rom	1.032m	2.451ms	1	1	100.00
		chip_sw_example_manufacturer	1.657m	3.133ms	1	1	100.00
		chip_sw_example_concurrency	2.439m	2.560ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.051m	6.297ms	1	1	100.00
V1	csr_rw	chip_csr_rw	4.636m	5.368ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	9.681m	8.630ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	58.511m	28.685ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	50.840s	2.071ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	58.511m	28.685ms	1	1	100.00
		chip_csr_rw	4.636m	5.368ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.540s	208.781us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.245m	4.292ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.245m	4.292ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.245m	4.292ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.643m	4.491ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.643m	4.491ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.411m	4.240ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.307m	4.506ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.072m	3.519ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	14.614m	7.256ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	16.440m	7.662ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.385m	3.754ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.042m	3.714ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.042m	3.714ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.362m	2.922ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.564m	3.267ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.165m	3.723ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.110m	2.518ms	1	1	100.00
		chip_tap_straps_testunlock0	3.566m	4.639ms	1	1	100.00
		chip_tap_straps_rma	2.419m	3.584ms	1	1	100.00
		chip_tap_straps_prod	1.733m	2.813ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.928m	2.326ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.561m	9.710ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.606m	5.810ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.606m	5.810ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.172m	7.593ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	29.508m	19.773ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.803m	3.605ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.094m	5.847ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.054m	18.704ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.536m	2.771ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.663m	6.816ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.210m	3.119ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.979m	13.341ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.823m	2.926ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.901m	5.128ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.163m	2.927ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.319m	2.851ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.681m	8.299ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.724m	4.833ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.483m	3.083ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.724m	4.833ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.237m	2.186ms	1	1	100.00
		chip_sw_aes_smoketest	3.103m	3.331ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.860m	3.460ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.926m	2.871ms	1	1	100.00
		chip_sw_csrng_smoketest	2.496m	3.020ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.698m	4.010ms	1	1	100.00
		chip_sw_gpio_smoketest	3.066m	2.670ms	1	1	100.00
		chip_sw_hmac_smoketest	2.761m	3.136ms	1	1	100.00
		chip_sw_kmac_smoketest	3.339m	2.870ms	1	1	100.00
		chip_sw_otbn_smoketest	15.008m	8.890ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.892m	4.539ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.512m	5.074ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.509m	2.599ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.053m	3.116ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.059m	2.821ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.080m	2.805ms	1	1	100.00
		chip_sw_uart_smoketest	2.046m	2.636ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.372m	2.579ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.900m	5.307ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.004h	60.139ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.736m	15.092ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.441m	5.731ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.697m	4.062ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.892m	3.380ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.899h	54.493ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.813h	55.226ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.595m	2.999ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.595m	2.999ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	58.511m	28.685ms	1	1	100.00
		chip_same_csr_outstanding	40.011m	29.773ms	1	1	100.00
		chip_csr_hw_reset	3.051m	6.297ms	1	1	100.00
		chip_csr_rw	4.636m	5.368ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	58.511m	28.685ms	1	1	100.00
		chip_same_csr_outstanding	40.011m	29.773ms	1	1	100.00
		chip_csr_hw_reset	3.051m	6.297ms	1	1	100.00
		chip_csr_rw	4.636m	5.368ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	16.920s	336.448us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.900s	37.734us	1	1	100.00
		xbar_smoke_large_delays	44.960s	7.395ms	1	1	100.00
		xbar_smoke_slow_rsp	49.250s	5.496ms	1	1	100.00
		xbar_random_zero_delays	13.750s	249.171us	1	1	100.00
		xbar_random_large_delays	2.932m	30.596ms	1	1	100.00
		xbar_random_slow_rsp	2.515m	18.652ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	10.440s	69.114us	1	1	100.00
		xbar_error_and_unmapped_addr	12.660s	414.553us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	11.670s	442.581us	1	1	100.00
		xbar_error_and_unmapped_addr	12.660s	414.553us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.010m	2.580ms	1	1	100.00
		xbar_access_same_device_slow_rsp	7.485m	53.707ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	15.450s	340.446us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	22.470s	304.183us	1	1	100.00
		xbar_stress_all_with_error	1.951m	2.546ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.157m	1.820ms	1	1	100.00
		xbar_stress_all_with_reset_error	2.028m	719.446us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.736m	15.092ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	36.080m	27.105ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	38.349m	14.726ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	30.672m	11.413ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	39.182m	15.377ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.646m	16.172ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.231m	14.952ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.752m	15.197ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.960s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	28.420s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	27.050s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.420s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.230s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	26.960s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	27.290s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	30.940s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	27.550s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.790s	10.200us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.520s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.140s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	27.540s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	24.970s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.520s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.370s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.570s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.050s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.350s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.380s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	27.160s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.120s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	27.130s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	26.710s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	27.750s	10.400us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.697m	11.562ms	1	1	100.00
		rom_e2e_asm_init_dev	36.470m	16.257ms	1	1	100.00
		rom_e2e_asm_init_prod	36.733m	15.651ms	1	1	100.00
		rom_e2e_asm_init_prod_end	36.780m	16.073ms	1	1	100.00
		rom_e2e_asm_init_rma	36.382m	14.372ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.011m	15.204ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.230m	15.004ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.646m	15.174ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.861m	15.634ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.946m	34.685ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.946m	34.685ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.360m	3.239ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.536m	2.771ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.134m	2.494ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.630m	3.284ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	10.710m	6.501ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.435m	2.275ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.391m	6.166ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.273m	4.233ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.951m	5.244ms	1	1	100.00
		chip_plic_all_irqs_10	4.586m	3.991ms	1	1	100.00
		chip_plic_all_irqs_20	6.416m	4.027ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.933m	3.802ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.467m	11.800ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	2.763m	3.722ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.260m	2.751ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.158m	11.178ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.193m	8.395ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	17.127m	8.259ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.571m	7.763ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.158h	255.438ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	2.870m	4.297ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	2.892m	4.539ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	2.870m	4.297ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.708m	9.281ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.708m	9.281ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.142m	7.469ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.378m	5.393ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.654m	5.448ms	1	1	100.00
		chip_sw_aes_idle	2.630m	3.284ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.684m	3.167ms	1	1	100.00
		chip_sw_kmac_idle	1.934m	1.866ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.321m	4.387ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	5.087m	5.266ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.183m	4.166ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.574m	3.314ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	13.087m	12.832ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.584m	3.665ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.250m	4.800ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.185m	3.728ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.156m	4.716ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.916m	3.712ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.335m	4.642ms	1	1	100.00
		chip_sw_ast_clk_outputs	10.172m	7.593ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	6.460m	8.985ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.185m	3.728ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.156m	4.716ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.803m	3.605ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.094m	5.847ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.054m	18.704ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.536m	2.771ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.663m	6.816ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.210m	3.119ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.979m	13.341ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.823m	2.926ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.901m	5.128ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.163m	2.927ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.109m	2.845ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.891m	4.918ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.567m	7.301ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	48.548m	23.897ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.208m	3.573ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.263m	2.975ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	15.209m	9.830ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.692m	2.927ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.911m	6.308ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.054m	19.698ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	29.146m	16.357ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.172m	7.593ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.094m	5.127ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.525m	3.718ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.273m	4.233ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	17.193m	8.395ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	17.253m	7.154ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.502m	2.957ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.445m	6.101ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.913m	3.328ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	46.340m	17.321ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	3.139m	2.538ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.644m	6.131ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.139m	2.538ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	17.253m	7.154ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.100m	2.520ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	20.065m	20.165ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.296m	5.496ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.094m	5.847ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.842m	4.413ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.803m	3.605ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	58.671m	44.084ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	20.065m	20.165ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	4.202m	3.785ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	13.606m	7.417ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.940m	4.377ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	58.671m	44.084ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.940m	4.377ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.940m	4.377ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.940m	4.377ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.940m	4.377ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.273m	4.233ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.346m	14.583ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.444m	4.858ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.992m	4.622ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.992m	4.622ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.351m	2.936ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.210m	3.119ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.684m	3.167ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.667m	2.702ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	18.867m	9.377ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.193m	4.516ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.428m	5.010ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.539m	4.891ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.563m	3.347ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	13.606m	7.417ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.979m	13.341ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	22.263m	10.658ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	10.710m	6.501ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	42.366m	15.542ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.636m	3.274ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.215m	3.719ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.823m	2.926ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	13.606m	7.417ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	8.329m	11.344ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	3.208m	3.551ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	16.987m	8.829ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.934m	1.866ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.391m	6.166ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.110m	2.518ms	1	1	100.00
		chip_tap_straps_rma	2.419m	3.584ms	1	1	100.00
		chip_tap_straps_prod	1.733m	2.813ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.617m	2.368ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	8.329m	11.344ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	8.329m	11.344ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	8.329m	11.344ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	20.864m	9.729ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.940m	4.377ms	1	1	100.00
		chip_sw_flash_rma_unlocked	58.671m	44.084ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.273m	3.942ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.285m	7.055ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.890m	7.133ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.127m	6.305ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.329m	11.344ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.606m	7.417ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.451m	8.494ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.609m	7.651ms	1	1	100.00
		chip_prim_tl_access	4.346m	14.583ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	6.460m	8.985ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.584m	3.665ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.250m	4.800ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.185m	3.728ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.156m	4.716ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.916m	3.712ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.335m	4.642ms	1	1	100.00
		chip_tap_straps_dev	2.110m	2.518ms	1	1	100.00
		chip_tap_straps_rma	2.419m	3.584ms	1	1	100.00
		chip_tap_straps_prod	1.733m	2.813ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.581m	13.065ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.168m	3.373ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.494m	3.637ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.384m	3.320ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.308m	2.376ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.556m	28.143ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.581m	13.065ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	56.074m	46.548ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	56.793m	50.533ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	6.476m	9.419ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.024h	45.989ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	18.556m	28.143ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.527m	2.985ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.245m	2.341ms	1	1	100.00
		rom_volatile_raw_unlock	1.080m	2.605ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.978m	16.892ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.054m	18.704ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.654m	5.448ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.654m	5.448ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.654m	5.448ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.036m	3.831ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	8.329m	11.344ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	20.065m	20.165ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.036m	3.831ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.606m	7.417ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.425m	4.261ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.357m	2.458ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	20.065m	20.165ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.036m	3.831ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.606m	7.417ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.425m	4.261ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.357m	2.458ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	8.329m	11.344ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	6.041m	5.811ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.617m	2.368ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.273m	3.942ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.285m	7.055ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.890m	7.133ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.127m	6.305ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.329m	11.344ms	1	1	100.00
		chip_prim_tl_access	4.346m	14.583ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.346m	14.583ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.371m	9.317ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.805m	10.145ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	18.171m	24.609ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.449m	7.474ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.405m	9.438ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.348m	7.277ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	15.930m	23.191ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	14.284m	13.797ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.708m	9.281ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	8.753m	9.249ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.625m	4.864ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.805m	10.145ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.817m	4.755ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	24.816m	35.889ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.144m	5.829ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.675m	6.306ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.620m	21.217ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.902m	8.540ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	16.907m	11.136ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	22.960m	31.014ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.891m	3.373ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.273m	4.233ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.451m	8.494ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.451m	8.494ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	16.907m	11.136ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.620m	21.217ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.625m	4.864ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.892m	4.539ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.340m	4.500ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.431m	4.227ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.459m	3.683ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.467m	11.800ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.712m	2.605ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.273m	4.233ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	17.127m	8.259ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.195m	4.844ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.948m	4.567ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.930m	3.290ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.357m	2.458ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.431m	4.227ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.431m	4.227ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	11.076m	10.639ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.617m	13.625ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.340m	4.500ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.424m	4.145ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.478m	6.338ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	2.419m	3.584ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.581m	13.065ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.951m	5.244ms	1	1	100.00
		chip_plic_all_irqs_10	4.586m	3.991ms	1	1	100.00
		chip_plic_all_irqs_20	6.416m	4.027ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.839m	2.536ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.170m	3.373ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.736m	15.092ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.788m	6.730ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.734m	3.240ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.567m	3.406ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.818m	3.104ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.425m	4.261ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.901m	5.128ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.324m	7.089ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.737m	7.038ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.609m	7.651ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.273m	4.233ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.606m	5.810ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.902m	8.540ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	16.311m	25.281ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.825m	2.034ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.453m	3.667ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.280m	4.298ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.311m	25.281ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.311m	25.281ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	38.696m	20.166ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	38.696m	20.166ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.766m	6.433ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.946m	34.685ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.291m	3.014ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.571m	2.532ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.902m	3.323ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.941m	4.398ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.318m	7.837ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.350h	31.705ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	28.510m	12.859ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	1.736m	2.809ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.020m	3.648ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.983m	2.923ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.362h	71.725ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.439m	5.306ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.191m	11.185ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.982m	11.459ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.416m	12.005ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.238m	4.266ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.568m	4.389ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.244m	4.274ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	17.938s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.914m	4.909ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.819m	2.982ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	14.984m	6.209ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	21.037m	9.515ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.231m	2.815ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.875m	5.240ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.068m	2.328ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.677m	4.950ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.921m	6.533ms	0	1	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.459m	5.546ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	16.907m	11.136ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.191m	11.185ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.982m	11.459ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.416m	12.005ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.992m	6.164ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.273m	4.233ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.434h	37.861ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.434h	37.861ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.394m	3.371ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.643m	4.491ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	50.483m	19.284ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.534m	3.354ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.515m	4.852ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.788m	3.277ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.480m	2.685ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.228m	3.610ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	17.769s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.499m	3.289ms	1	1	100.00
		TOTAL			286	325	88.00

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.92788863844075585404901617647287125575367521290434611826993044875809740461521
    Line 625, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.15927606633593895822951762244092165888557173434452187439438939111545898319776
    Line 709, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.36948080173905793826216859797310106135878092529253938526606922287036815956666
    Line 631, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.28731484397652213161624724553272792639242743932102604939922930127188860811071
    Line 699, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.109542288451424018993087591352410940938975910986481999704868650536922737610342
    Line 668, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.97307413990766029271167307103030792050494879220463087855450558536430572539296
    Line 501, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.111353908552165308944783993292173774734858046168028574997934406475222522238142
    Line 489, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.67299032084798374454231315237709971211991251901761980691598182767821696248110
    Line 677, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.46490770199461610216353159400287736570319410247139257245464622774512567765596
    Line 619, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.83726721375611496835370928677182861284875983714698607345639896589264061189903
    Line 586, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.105115188780153954219318948514277751680562742691221418468974286155889737320395
    Line 768, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.43750890302497198841715547803881367351741388384457674394077842116983135247560
    Line 666, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.72508090906128521265467526486112458724412213645264833069852051843145367339629
    Line 690, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.68511237426859449333715986200398370708793296068266573734325349316003603916241
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 2.582s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.79152629194789152623811175120006132741700284587602831759156014104556613380410
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 8.044s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.100431162036440514955259672482503770270951064161445730932470441957908901940132
    Line 736, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.99193116501054589945333370160701516560159106096870923769404525066688747139235
    Line 611, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.73654613579239561163061789636015429789406029819161207475688944967582039020079
    Line 837, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.51358723697046395197966182796070412038038479339732075969598739942138359708988
    Line 658, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.80117018387642221758042394033703617071042370088162675092097850184902211324093
    Line 423, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3239.719140 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3239.719140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@86245) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.99807021041482570279334780613731930252549975761458195117121078758894422079080
Line 458, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4226.586750 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@86245) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4226.586750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.36488890414454957197330302032190180296356981341030957243265962526145109260360
    Line 484, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34684.569897 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34684.569897 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.36693646664146668469410162451849129302242576538163382021999697729410823291265
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2275.330568 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 2275.330568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.67535454891936934900777625147066861882155381920716050942742318175991672273043
    Line 418, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2751.092620 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2751.092620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.74356931181519882045393610186631024536903194253850700190647457868979253853664
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2957.178261 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2957.178261 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@94789) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.95418307055492670501867422428407698625539483130041042390862738827228149097742
Line 220, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2999.028540 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@94789) { a_addr: 'h1041c  a_data: 'hd317619f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h1a93d  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2999.028540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 1 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.7255929682343662742445943253714190252872124335339767325432014910467020017267
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_ERROR @ 6532.991128 us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 6532.991128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.89550577374214164997304459837831643778217144101532378172895673286875022759552
    Line 425, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 4061.850000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 4061.850000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.5006304347406962169097298586119548759230952965020311097940411741702645765675
    Line 427, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3379.825000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3379.825000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.48048974569247817943175247869417955388414253662103741892137506500762746878158
    Line 444, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19773.288469 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19773.288469 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.76834304004900104231422432232959047990914848698785562500483731979653722904197
    Line 783, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.28559683013443047286021082141211517544423502882565767898050014522354013492753
    Line 701, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32109) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.84885188803985703483709358387831103194753845755527394702992808328338972106616
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2071.115800 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32109) { a_addr: 'h10400  a_data: 'hc1a71a63  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h195da  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2071.115800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---