ADC_CTRL Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	4.180s	5.574ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.310s	688.946us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.630s	362.299us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.238m	26.789ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.520s	1.199ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.640s	419.362us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.630s	362.299us	1	1	100.00
		adc_ctrl_csr_aliasing	3.520s	1.199ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	4.399m	165.169ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	4.042m	489.783ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	1.398m	168.591ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	3.404m	494.130ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	55.520s	175.299ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	11.046m	408.431ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.360m	331.414ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	7.288m	2.000s	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.880s	3.016ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	54.330s	33.027ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.397m	88.552ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	1.106m	82.958ms	0	1	0.00
V2	alert_test	adc_ctrl_alert_test	2.200s	497.245us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.670s	523.389us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.640s	394.095us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.640s	394.095us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.310s	688.946us	1	1	100.00
		adc_ctrl_csr_rw	1.630s	362.299us	1	1	100.00
		adc_ctrl_csr_aliasing	3.520s	1.199ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	7.860s	4.116ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.310s	688.946us	1	1	100.00
		adc_ctrl_csr_rw	1.630s	362.299us	1	1	100.00
		adc_ctrl_csr_aliasing	3.520s	1.199ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	7.860s	4.116ms	1	1	100.00
V2		TOTAL			14	16	87.50
V2S	tl_intg_err	adc_ctrl_sec_cm	13.930s	7.593ms	1	1	100.00
		adc_ctrl_tl_intg_err	7.680s	4.440ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	7.680s	4.440ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.890s	5.673ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			23	25	92.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.19690267708973513743024692663375308570271909102146305749970874037826233781019
      Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 1 failures:

  • Test adc_ctrl_stress_all has 1 failures.

    • 0.adc_ctrl_stress_all.102237127450172610493323715195296442145271489389302145034176004473142003799278
      Line 147, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 82958253608 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 82958253608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---