EDN Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.750s 208.033us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.720s 45.266us 1 1 100.00
V1 csr_rw edn_csr_rw 1.810s 22.701us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.530s 188.967us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.840s 39.098us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.180s 95.486us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.810s 22.701us 1 1 100.00
edn_csr_aliasing 1.840s 39.098us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.850s 116.617us 1 1 100.00
V2 csrng_commands edn_genbits 1.850s 116.617us 1 1 100.00
V2 genbits edn_genbits 1.850s 116.617us 1 1 100.00
V2 interrupts edn_intr 1.720s 22.476us 1 1 100.00
V2 alerts edn_alert 1.910s 32.177us 1 1 100.00
V2 errs edn_err 1.930s 69.802us 1 1 100.00
V2 disable edn_disable 1.580s 24.621us 1 1 100.00
edn_disable_auto_req_mode 1.770s 74.999us 1 1 100.00
V2 stress_all edn_stress_all 2.410s 72.904us 1 1 100.00
V2 intr_test edn_intr_test 1.750s 22.576us 1 1 100.00
V2 alert_test edn_alert_test 1.540s 75.370us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.280s 194.636us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.280s 194.636us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.720s 45.266us 1 1 100.00
edn_csr_rw 1.810s 22.701us 1 1 100.00
edn_csr_aliasing 1.840s 39.098us 1 1 100.00
edn_same_csr_outstanding 2.110s 116.370us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.720s 45.266us 1 1 100.00
edn_csr_rw 1.810s 22.701us 1 1 100.00
edn_csr_aliasing 1.840s 39.098us 1 1 100.00
edn_same_csr_outstanding 2.110s 116.370us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.210s 273.760us 1 1 100.00
edn_tl_intg_err 3.390s 152.300us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.570s 39.064us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.910s 32.177us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.210s 273.760us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.210s 273.760us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.210s 273.760us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.210s 273.760us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.910s 32.177us 1 1 100.00
edn_sec_cm 4.210s 273.760us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.910s 32.177us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.390s 152.300us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets