HMAC Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 13.590s 1.626ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.700s 70.118us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.770s 15.070us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.980s 217.589us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.490s 626.711us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 10.898m 92.198ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.770s 15.070us 1 1 100.00
hmac_csr_aliasing 6.490s 626.711us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 41.850s 990.914us 1 1 100.00
V2 back_pressure hmac_back_pressure 1.020m 1.566ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.386m 7.015ms 1 1 100.00
hmac_test_sha384_vectors 6.962m 39.859ms 1 1 100.00
hmac_test_sha512_vectors 21.340s 892.291us 1 1 100.00
hmac_test_hmac256_vectors 8.780s 923.072us 1 1 100.00
hmac_test_hmac384_vectors 7.980s 405.375us 1 1 100.00
hmac_test_hmac512_vectors 14.590s 1.296ms 1 1 100.00
V2 burst_wr hmac_burst_wr 16.880s 1.711ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.745m 2.004ms 1 1 100.00
V2 error hmac_error 42.350s 3.385ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.534m 2.920ms 1 1 100.00
V2 save_and_restore hmac_smoke 13.590s 1.626ms 1 1 100.00
hmac_long_msg 41.850s 990.914us 1 1 100.00
hmac_back_pressure 1.020m 1.566ms 1 1 100.00
hmac_datapath_stress 4.745m 2.004ms 1 1 100.00
hmac_burst_wr 16.880s 1.711ms 1 1 100.00
hmac_stress_all 45.750s 4.904ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 13.590s 1.626ms 1 1 100.00
hmac_long_msg 41.850s 990.914us 1 1 100.00
hmac_back_pressure 1.020m 1.566ms 1 1 100.00
hmac_datapath_stress 4.745m 2.004ms 1 1 100.00
hmac_wipe_secret 1.534m 2.920ms 1 1 100.00
hmac_test_sha256_vectors 3.386m 7.015ms 1 1 100.00
hmac_test_sha384_vectors 6.962m 39.859ms 1 1 100.00
hmac_test_sha512_vectors 21.340s 892.291us 1 1 100.00
hmac_test_hmac256_vectors 8.780s 923.072us 1 1 100.00
hmac_test_hmac384_vectors 7.980s 405.375us 1 1 100.00
hmac_test_hmac512_vectors 14.590s 1.296ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 13.590s 1.626ms 1 1 100.00
hmac_long_msg 41.850s 990.914us 1 1 100.00
hmac_back_pressure 1.020m 1.566ms 1 1 100.00
hmac_datapath_stress 4.745m 2.004ms 1 1 100.00
hmac_burst_wr 16.880s 1.711ms 1 1 100.00
hmac_error 42.350s 3.385ms 1 1 100.00
hmac_wipe_secret 1.534m 2.920ms 1 1 100.00
hmac_test_sha256_vectors 3.386m 7.015ms 1 1 100.00
hmac_test_sha384_vectors 6.962m 39.859ms 1 1 100.00
hmac_test_sha512_vectors 21.340s 892.291us 1 1 100.00
hmac_test_hmac256_vectors 8.780s 923.072us 1 1 100.00
hmac_test_hmac384_vectors 7.980s 405.375us 1 1 100.00
hmac_test_hmac512_vectors 14.590s 1.296ms 1 1 100.00
hmac_stress_all 45.750s 4.904ms 1 1 100.00
V2 stress_all hmac_stress_all 45.750s 4.904ms 1 1 100.00
V2 alert_test hmac_alert_test 1.480s 44.108us 1 1 100.00
V2 intr_test hmac_intr_test 1.550s 45.697us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.410s 479.714us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.410s 479.714us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.700s 70.118us 1 1 100.00
hmac_csr_rw 1.770s 15.070us 1 1 100.00
hmac_csr_aliasing 6.490s 626.711us 1 1 100.00
hmac_same_csr_outstanding 3.200s 159.167us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.700s 70.118us 1 1 100.00
hmac_csr_rw 1.770s 15.070us 1 1 100.00
hmac_csr_aliasing 6.490s 626.711us 1 1 100.00
hmac_same_csr_outstanding 3.200s 159.167us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.740s 330.057us 1 1 100.00
hmac_tl_intg_err 4.060s 135.706us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.060s 135.706us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 13.590s 1.626ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.140s 131.296us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.277m 46.621ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.170s 74.009us 1 1 100.00
TOTAL 28 28 100.00