I2C Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: `d7d3545`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	20.940s	3.156ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	11.980s	4.482ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.840s	79.385us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.870s	61.123us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.220s	113.795us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.910s	55.633us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.820s	44.383us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.870s	61.123us	1	1	100.00
		i2c_csr_aliasing	1.910s	55.633us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	6.770s	909.344us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	2.167m	15.625ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	6.409m	17.806ms	1	1	100.00
V2	host_override	i2c_host_override	1.870s	46.550us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.151m	12.772ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	58.120s	1.431ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.860s	113.387us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.290s	333.559us	1	1	100.00
		i2c_host_fifo_reset_rx	5.440s	132.565us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	27.040s	10.214ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	16.150s	705.026us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.590s	165.529us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.060s	1.824ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.542m	23.999ms	0	1	0.00
V2	target_maxperf	i2c_target_perf	3.270s	928.624us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	8.740s	2.113ms	1	1	100.00
		i2c_target_intr_smoke	4.880s	2.575ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.020s	633.313us	1	1	100.00
		i2c_target_fifo_reset_tx	1.780s	219.022us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.756m	55.252ms	1	1	100.00
		i2c_target_stress_rd	8.740s	2.113ms	1	1	100.00
		i2c_target_intr_stress_wr	4.000s	3.801ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	8.670s	5.402ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.003m	4.368ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.550s	3.602ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.990s	258.304us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.780s	235.237us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.800s	589.323us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	6.409m	17.806ms	1	1	100.00
		i2c_host_perf_precise	1.710s	65.582us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	16.150s	705.026us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.160s	161.664us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.030s	2.128ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.720s	1.079ms	1	1	100.00
		i2c_target_nack_txstretch	2.040s	328.880us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.950s	448.965us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.340s	399.853us	1	1	100.00
V2	alert_test	i2c_alert_test	1.500s	39.034us	1	1	100.00
V2	intr_test	i2c_intr_test	1.430s	110.728us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.400s	32.206us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.400s	32.206us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.840s	79.385us	1	1	100.00
		i2c_csr_rw	1.870s	61.123us	1	1	100.00
		i2c_csr_aliasing	1.910s	55.633us	1	1	100.00
		i2c_same_csr_outstanding	1.850s	129.516us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.840s	79.385us	1	1	100.00
		i2c_csr_rw	1.870s	61.123us	1	1	100.00
		i2c_csr_aliasing	1.910s	55.633us	1	1	100.00
		i2c_same_csr_outstanding	1.850s	129.516us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.420s	98.881us	1	1	100.00
		i2c_sec_cm	1.710s	129.246us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.420s	98.881us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	16.000s	867.171us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.930s	583.624us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	12.890s	1.102ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.13117500087810302594544005784786993337698831592072708493507626385303163756070
    Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 867171463 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 867171463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.8775816030874498813047619825131838174969949023600610387820372962244399311259
    Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1101604264 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1101604264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.27397524437903715966512342172173613092992380260543231313998954907201997549993
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 583623984 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 237 [0xed])
  UVM_INFO @ 583623984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all has 1 failures.
  - 0.i2c_target_stress_all.70576491631469573409644254581143389470939043586547799622723215840454481578071
    Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 23998795766 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 23998795766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.20285043296596092316880093898904264679660419657330878073565347197514495241375
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 165529129 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @10925