KEYMGR Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.830s	35.047us	1	1	100.00
V1	random	keymgr_random	3.820s	342.979us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.910s	138.913us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.260s	29.655us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	7.460s	854.152us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.320s	3.597ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.890s	17.151us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.260s	29.655us	1	1	100.00
		keymgr_csr_aliasing	8.320s	3.597ms	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	3.740s	72.235us	1	1	100.00
V2	sideload	keymgr_sideload	3.030s	49.490us	1	1	100.00
		keymgr_sideload_kmac	3.710s	127.132us	1	1	100.00
		keymgr_sideload_aes	5.840s	366.423us	1	1	100.00
		keymgr_sideload_otbn	4.020s	692.535us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.070s	65.129us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.780s	82.531us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.940s	38.067us	0	1	0.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.010s	40.119us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	5.950s	970.205us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.580s	172.037us	1	1	100.00
V2	stress_all	keymgr_stress_all	8.970s	225.151us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.580s	59.890us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.700s	41.013us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.970s	112.872us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.970s	112.872us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.910s	138.913us	1	1	100.00
		keymgr_csr_rw	2.260s	29.655us	1	1	100.00
		keymgr_csr_aliasing	8.320s	3.597ms	1	1	100.00
		keymgr_same_csr_outstanding	2.170s	197.248us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.910s	138.913us	1	1	100.00
		keymgr_csr_rw	2.260s	29.655us	1	1	100.00
		keymgr_csr_aliasing	8.320s	3.597ms	1	1	100.00
		keymgr_same_csr_outstanding	2.170s	197.248us	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	10.960s	514.649us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	10.960s	514.649us	1	1	100.00
		keymgr_tl_intg_err	5.000s	523.157us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.940s	319.689us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.940s	319.689us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.940s	319.689us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.940s	319.689us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.080s	462.749us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	10.960s	514.649us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	10.960s	514.649us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.000s	523.157us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.940s	319.689us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.740s	72.235us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.820s	342.979us	1	1	100.00
		keymgr_csr_rw	2.260s	29.655us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.820s	342.979us	1	1	100.00
		keymgr_csr_rw	2.260s	29.655us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.820s	342.979us	1	1	100.00
		keymgr_csr_rw	2.260s	29.655us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.780s	82.531us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	5.950s	970.205us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	5.950s	970.205us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.820s	342.979us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.020s	169.607us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	10.960s	514.649us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	10.960s	514.649us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	10.960s	514.649us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.140s	32.395us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.780s	82.531us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	10.960s	514.649us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	10.960s	514.649us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	10.960s	514.649us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.140s	32.395us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.140s	32.395us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	10.960s	514.649us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.140s	32.395us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	10.960s	514.649us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.140s	32.395us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	6.620s	157.317us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:263) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
  • Test keymgr_kmac_rsp_err has 1 failures.

    • 0.keymgr_kmac_rsp_err.35756337456232108317504894802655768561642417501432491934862605628709789168837
      Line 323, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  38066802 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @  38066802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---