KMAC/MASKED Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	33.390s	4.292ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.900s	126.918us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.630s	141.883us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.780s	3.431ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.990s	1.512ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.490s	172.753us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.630s	141.883us	1	1	100.00
		kmac_csr_aliasing	6.990s	1.512ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.550s	32.174us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.070s	39.735us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	6.967m	5.971ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.995m	50.188ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.466m	71.792ms	1	1	100.00
		kmac_test_vectors_sha3_256	32.910s	7.683ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.358m	45.872ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.837m	45.294ms	1	1	100.00
		kmac_test_vectors_shake_128	2.814m	16.628ms	1	1	100.00
		kmac_test_vectors_shake_256	27.859m	83.217ms	1	1	100.00
		kmac_test_vectors_kmac	3.100s	104.990us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.420s	143.405us	1	1	100.00
V2	sideload	kmac_sideload	2.995m	6.180ms	1	1	100.00
V2	app	kmac_app	1.748m	4.619ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	40.930s	4.821ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.291m	25.153ms	1	1	100.00
V2	error	kmac_error	6.459m	52.626ms	1	1	100.00
V2	key_error	kmac_key_error	10.700s	1.328ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	5.500s	202.426us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.660s	16.224us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.930s	102.250us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	6.030s	2.711ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.940s	101.263us	1	1	100.00
V2	stress_all	kmac_stress_all	24.574m	78.794ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.720s	12.185us	1	1	100.00
V2	alert_test	kmac_alert_test	1.680s	28.681us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.440s	760.858us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.440s	760.858us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.900s	126.918us	1	1	100.00
		kmac_csr_rw	1.630s	141.883us	1	1	100.00
		kmac_csr_aliasing	6.990s	1.512ms	1	1	100.00
		kmac_same_csr_outstanding	3.270s	118.183us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.900s	126.918us	1	1	100.00
		kmac_csr_rw	1.630s	141.883us	1	1	100.00
		kmac_csr_aliasing	6.990s	1.512ms	1	1	100.00
		kmac_same_csr_outstanding	3.270s	118.183us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.270s	98.464us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.270s	98.464us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.270s	98.464us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.270s	98.464us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.910s	29.407us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	30.430s	8.710ms	1	1	100.00
		kmac_tl_intg_err	1.700s	31.300us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.700s	31.300us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.940s	101.263us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	33.390s	4.292ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.995m	6.180ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.270s	98.464us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	30.430s	8.710ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	30.430s	8.710ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	30.430s	8.710ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	33.390s	4.292ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.940s	101.263us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	30.430s	8.710ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.523m	19.023ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	33.390s	4.292ms	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	25.610s	1.663ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.37160709919911733492794307597932150855794986228616135528280171687626820809290
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
        UVM_ERROR @  29407002 ps: (kmac_csr_assert_fpv.sv:520) [ASSERT FAILED] prefix_5_rd_A
        UVM_INFO @  29407002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.33327510053749673450626103238930309763615670336709169200201063378082829559932
      Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
        UVM_ERROR @  31299988 ps: (kmac_csr_assert_fpv.sv:490) [ASSERT FAILED] entropy_period_rd_A
        UVM_INFO @  31299988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.27101051891129669144930362495802736049214300581753377944447051013802680889913
      Line 139, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1663223753 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1663223753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---