KMAC/UNMASKED Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	33.770s	11.585ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.620s	36.763us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.800s	59.331us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.610s	496.551us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.840s	1.073ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.500s	172.074us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.800s	59.331us	1	1	100.00
		kmac_csr_aliasing	7.840s	1.073ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.550s	33.208us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.330s	31.185us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	20.627m	19.294ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.956m	38.251ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	17.234m	17.209ms	1	1	100.00
		kmac_test_vectors_sha3_256	22.260s	1.145ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.490s	3.100ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.520s	7.447ms	1	1	100.00
		kmac_test_vectors_shake_128	1.947m	3.582ms	1	1	100.00
		kmac_test_vectors_shake_256	1.279m	4.754ms	1	1	100.00
		kmac_test_vectors_kmac	2.520s	64.885us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.660s	36.341us	1	1	100.00
V2	sideload	kmac_sideload	24.120s	7.376ms	1	1	100.00
V2	app	kmac_app	32.470s	2.718ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	42.390s	8.054ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	21.550s	6.190ms	1	1	100.00
V2	error	kmac_error	6.250s	979.865us	1	1	100.00
V2	key_error	kmac_key_error	2.820s	1.584ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	43.130s	10.085ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	22.690s	812.734us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	7.680s	730.428us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	10.700s	1.169ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	3.480s	1.238ms	1	1	100.00
V2	stress_all	kmac_stress_all	15.155m	63.179ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.650s	72.264us	1	1	100.00
V2	alert_test	kmac_alert_test	1.640s	13.072us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.180s	58.549us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.180s	58.549us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.620s	36.763us	1	1	100.00
		kmac_csr_rw	1.800s	59.331us	1	1	100.00
		kmac_csr_aliasing	7.840s	1.073ms	1	1	100.00
		kmac_same_csr_outstanding	2.650s	38.397us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.620s	36.763us	1	1	100.00
		kmac_csr_rw	1.800s	59.331us	1	1	100.00
		kmac_csr_aliasing	7.840s	1.073ms	1	1	100.00
		kmac_same_csr_outstanding	2.650s	38.397us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.960s	105.006us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.960s	105.006us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.960s	105.006us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.960s	105.006us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.970s	343.827us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	19.060s	10.290ms	1	1	100.00
		kmac_tl_intg_err	1.910s	11.198us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.910s	11.198us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	3.480s	1.238ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	33.770s	11.585ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	24.120s	7.376ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.960s	105.006us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	19.060s	10.290ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	19.060s	10.290ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	19.060s	10.290ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	33.770s	11.585ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	3.480s	1.238ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	19.060s	10.290ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.450m	2.478ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	33.770s	11.585ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	53.110s	6.157ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.30777518473759996270939524257890912470126643187694399981755496963962509210615
      Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10085271405 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xeb182000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10085271405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.47565259058352764381036093634567564006915056560478039373254029579571727563912
      Line 115, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6157372585 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6157372585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.71022588899729834271394980275597018922698998520066821362699055432832450699011
      Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @  11198264 ps: (kmac_csr_assert_fpv.sv:510) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @  11198264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---